IP Library Granted Patent US 8,168,522
Granted Patent B2
US 8,168,522 · App. 12/718,449 · Granted May 1, 2012

Method for fabricating semiconductor device

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Quick Facts
Patent No.
US 8,168,522
App. No.
12/718,449
Granted
May 1, 2012
Kind
B2
Abstract

An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film.

Claims (32)

1. A method for fabricating a semiconductor device, comprising:

forming a gate insulating film on a semiconductor substrate,

forming a metal film on the gate insulating film,

depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film,

forming a silicon film on the metal-silicon compound film, and

etching the metal film, the metal-silicon compound film, and the silicon film.

2. The method of claim 1 , further comprising:

removing an oxide film formed on a surface of the metal-silicon compound film before the silicon film is formed.

3. The method of claim 1 , wherein

the metal film is at least one of a nitride of elements in the Groups IV, V and VI, a carbide of elements in the Groups IV, V and VI, a silicon nitride, of elements in the Groups IV, V and VI and, a silicon carbide, of elements in the Groups IV, V and VI.

4. The method of claim 1 , wherein

the metal-silicon compound film includes at least one of metals in the Groups IV, V or VI.

5. The method of claim 1 , wherein

each of the metal film and the metal-silicon compound film includes at least one of metals in the same Group of Groups IV, V and VI.

6. The method of claim 1 , wherein

the semiconductor substrate has a p-type MOS area and an n-type MOS area.

7. The method of claim 6 , further comprising:

forming a SiGe layer on the p-type MOS area of the semiconductor substrate before forming the gate insulating film on the semiconductor substrate.

8. The method of claim 1 , further comprising:

forming an interfacial layer on the semiconductor substrate before forming the gate insulating layer.

9. The method of claim 6 , further comprising:

forming an interfacial layer on the n-type MOS area of the semiconductor substrate and on the SiGe layer on the p-type MOS area before forming the gate insulating layer.

10. The method of claim 6 , further comprising:

forming a threshold control layer on the gate insulating film in the n-type MOS area before the metal film is formed onto the gate insulating film.

11. The method of claim 10 , wherein

the threshold control layer on the n-type MOS area includes magnesium or lanthanum.

12. The method of claim 6 , further comprising:

forming a threshold control layer on the gate insulating film in the p-type MOS area before the metal film is formed on the gate insulating film.

13. The method of claim 12 , wherein

the threshold control layer in the p-type MOS area includes alumina.

14. The method of claim 1 , wherein

the gate insulating film is at least one of oxides of Hf, Zr, Ti, Ta, Al, Sr, Y and La, silicon oxides of Hf, Zr, Ti, Ta, Al, Sr and Y, and laminated films including the oxides and/or the silicon oxides.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 11, 2017
From: TOSHIBA CORPORATION
To: MICROSOFT TECHNOLOGY LICENSING, LLC
Reel/Frame 041333/0955 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2010
From: NAKAJIMA, KAZUAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024036/0612 →