Victim net crosstalk reduction

1. A circuit analysis tool, enabled with software instructions stored in a non-transitory computer-readable medium and executed by a processor, for minimizing circuit crosstalk, the instructions comprising:

providing a first circuit connected to an output node having a last gate with a plurality of inputs and an output;

calculating a first circuit victim net delay range having a minimum delay (Vmin) and a maximum delay (Vmax);

providing a second circuit having an output connected to the output node to supply an aggressor net delay range (A 1 ) having a minimum delay (A 1 min ) and a maximum delay (A 1 max ), where the aggressor net delay range at least partially overlaps the victim net delay range;

without increasing the value of Vmax, shrinking the first circuit victim net delay range; and,

minimizing crosstalk between the first and second circuits without an increase in first circuit maximum signal delay.

2. The instructions of claim 1 wherein calculating the first circuit victim net delay range includes:

deriving a range of signal delays (Imin and Imax) for each last gate input (j);

in response to deriving the smallest Imin value and the largest Imax value, calculating the range of signal delays for the gate output;

wherein shrinking the victim net delay range includes:

for each input (j), finding the difference between the largest Imax value and the I j max value for that input; and,

adding a circuit delay prior to each gate input, equal to the difference.

3. The instructions of claim 2 shrinking the first circuit victim net delay range includes eliminating the overlap between the victim net delay range and aggressor net delay range; and,

wherein minimizing the crosstalk includes eliminating crosstalk between the first and second circuits.

4. The instructions of claim 2 further comprising:

selecting a margin value; and,

wherein shrinking the victim net delay range further includes finding the difference between Vmax and Vmin; and,

wherein adding the circuit delays prior to each gate input includes adding the circuit delays if the difference is greater than the margin value.

5. The instructions of claim 1 wherein providing the second circuit includes providing a second circuit with a last gate having a plurality of inputs and an output; and,

the instructions further comprising:

shrinking the second circuit aggressor net delay range (A 1 ) without increasing the value of A 1 max.

6. The instructions of claim 5 further comprising:

calculating the second circuit aggressor net (A 1 ) delay range as follows:

deriving a range of signal delays (Imin and Imax) for each last gate input (j);

in response to deriving the smallest Imin value and the largest Imax value, calculating the range of signal delays for the gate output;

wherein shrinking the second circuit aggressor net de ay range (A 1 ) includes:

for each input (j), finding the difference between the largest Imax value and the I j max value for that input; and,

adding a circuit delay prior to each gate input, equal to the difference.

7. The instructions of claim 1 further comprising:

providing a third circuit having the output comiected to the output node to supply an aggressor net delay range (A 2 ) at least partially overlapping the victim net delay range and the aggressor net delay range (A 1 );

adding a delay to a circuit selected from a group consisting of the second and third circuits, such that A 1 does not overlap A 2 .

8. The instructions of claim 7 further comprising:

shrinking the aggressor net delay range of a circuit selected from a group consisting of the second circuit, the third circuit, and both the second and third circuits.

9. The instructions of claim 1 further comprising:

providing a third circuit having the output comiected to the output node to supply an aggressor net signal delay range (A 2 ) at least partially overlapping the victim net delay range and the aggressor net delay range (A 1 );

the instructions further comprising:

shrinking the aggressor net delay range of a circuit selected from a group consisting of the second circuit, the third circuit, and both the second and third circuits.

10. A circuit analysis tool, enabled with software instructions stored in a non-transitory computer-readable medium and executed by a processor, for minimizing circuit crosstalk exposure, the instructions comprising:

providing a first circuit connected to an output node having a last gate with a plurality of inputs and an output;

providing a second circuit having an output connected to the output node to supply an aggressor net delay range (A 1 ) having a minimum delay (A 1 min ) and a maximum delay (A 1 max ), where the aggressor net delay range at least partially overlaps the victim net delay range;

providing a third circuit having the output connected to the output node to supply an aggressor net delay range (A 2 ) at least partially overlapping the victim net delay range and the aggressor net delay range (A 1 );

calculating a first circuit victim net delay range having a minimum delay (Vmin) and a maximum delay (Vmax);

adding a delay to a circuit selected from a group consisting of the second and third circuits, such that A 1 does not overlap A 2 ;

minimizing crosstalk between the first circuit, and the second and third circuits, without an increase in the first circuit maximum signal delay.