SWITCH CIRCUIT

1 . A switch circuit comprising:

an input section;

an output section;

a first series section having an output and comprising at least a first 4-terminal FET connected between said input section and said output section through the output of said first series section;

a first shunt section comprising at least a second 4-terminal FET connected between an output of said first series section and a ground;

a first control terminal section connected with a gate of said first 4-terminal FET;

a second control terminal section connected with a gate of said second 4-terminal FET;

a back gate control terminal section connected with a back gate of each of said first and second 4-terminal FETs; and

a bias power supply section configured to apply a reverse bias voltage between said back gate control terminal section and said ground.

2 . The switch circuit according to claim 1 , wherein said bias voltage is applied in a reverse direction of a source—back gate parasitic diode and a drain—back gate parasitic diode in each of said first and second 4-terminal FETs.

3 . The switch circuit according to claim 1 , wherein said first series section comprises:

a resistance connected between said back gate of said first 4-terminal FET and said back gate control terminal section, and

wherein said first shunt section comprises:

a resistance connected between said back gate of said second 4-terminal FET and said back gate control terminal section.

4 . The switch circuit according to claim 1 , wherein said first series section comprises:

a plurality of said first 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of first 4-terminal FETs is connected with said first control terminal, and

wherein a back gate of each of said plurality of first 4-terminal FETs is connected with said back gate control terminal section.

5 . The switch circuit according to claim 1 , wherein said first shunt section comprises:

a plurality of said second 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of second 4-terminal FETs is connected with said second control terminal, and

wherein a back gate of each of said plurality of second 4-terminal FETs is connected with said back gate control terminal section.

6 . The switch circuit according to claim 1 , further comprising:

a second series section comprising at least a third 4-terminal FET connected between the output of said first series section and said output section;

a second shunt section comprising at least a fourth 4-terminal FET connected with said output section; and

a termination resistance connected between said second shunt section and said ground,

wherein a gate of said third 4-terminal FET is connected to said first control terminal section, and a gate of said fourth 4-terminal FET is connected to said second control terminal section,

wherein a back gate of each of said third and fourth 4-terminal FETs is connected to said back gate control terminal section.

7 . The switch circuit according to claim 6 , wherein said second series section comprises;

a resistance connected between said back gate of said third 4-terminal FET and said back gate control terminal section, and

wherein said second shunt section comprises:

a resistance connected between said back gate of said fourth 4-terminal FET and said back gate control terminal section.

8 . The switch circuit according to claim 6 , wherein said second series section comprises:

a plurality of said third 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of third 4-terminal FETs is connected with said first control terminal, and

wherein a back gate of each of said plurality of third 4-terminal FETs is connected with said back gate control terminal section.

9 . The switch circuit according to claim 6 , wherein said second shunt section comprises:

a plurality of said fourth 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of fourth 4-terminal FETs is connected with said second control terminal, and

wherein a back gate of each of said plurality of fourth 4-terminal FETs is connected with said back gate control terminal section.

10 . The switch circuit according to claim 1 , wherein said bias power supply section comprises:

a DC-DC converter circuit configured to convert an input voltage into a fixed voltage.

11 . The switch circuit according to claim 1 , further comprising:

an inverter circuit section having an input section connected with said first control terminal and an output section connected with said second control terminal.

12 . The switch circuit according to claim 1 , further comprising:

a second output section;

a second back gate control terminal section;

a second bias power supply section configured to apply a reverse bias voltage between said second back gate control terminal and said ground;

a second series section comprising at least a third 4-terminal FET connected between said input section and said second output section; and

a second shunt section comprising at least a fourth 4-terminal FET connected with said second output section and said ground,

wherein a gate of said third 4-terminal FET is connected to said first control terminal section, and a gate of said fourth 4-terminal FET is connected to said second control terminal section,

wherein a back gate of said third 4-terminal FET is connected to said back gate control terminal section, and a back gate of said fourth 4-terminal FET is connected to said second back gate control terminal section.

13 . The switch circuit according to claim 12 , wherein said second series section comprises:

a resistance connected between said back gate of said third 4-terminal FET and said back gate control terminal section, and

wherein said shunt section comprises:

a resistance connected between said back gate of said fourth 4-terminal FET and said second back gate control terminal section.

14 . The switch circuit according to claim 12 , wherein said second series section comprises:

a plurality of said third 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of third 4-terminal FETs is connected with said first control terminal, and

wherein a back gate of each of said plurality of third 4-terminal FETs is connected with said back gate control terminal section.

15 . The switch circuit according to claim 12 , wherein said second shunt section comprises:

a plurality of said fourth 4-terminal FETs which are connected in series,

wherein a gate of each of said plurality of fourth 4-terminal FETs is connected with said second control terminal, and

wherein a back gate of each of said plurality of fourth 4-terminal FETs is connected with said second back gate control terminal section.

16 . A matrix switch circuit comprising:

n input sections, where n is an integer larger than 1;

m output sections, where m is an integer larger than 1;

a back gate control terminal section;

a bias power supply section configured to apply a reverse bias voltage between said back gate control terminal section and said ground,

(n×m) switch circuits; and

(n×m) control terminals,

wherein an (i, j) th (n≧i≧2, m≧j≧2) of said (n×m) switch circuits is connected with an i th one of said n input sections, a j th one of said m output sections, and an (i, j) th one of said (n×m) control terminals,

wherein each of said (n×m) switch circuits comprises:

a first series section having an output and comprising at least a first 4-terminal FET connected between a corresponding one of said n input sections and a corresponding one of said m output sections through the output of said first series section; and

a first shunt section comprising at least a second 4-terminal FET connected between an output of said first series section and a ground,

wherein a gate of each of said first and second 4-terminal FETS is connected with said back gate control terminal section.