Semiconductor memory device
A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.
1. A semiconductor memory device comprising:
a substrate;
a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film;
a first floating gate formed on the first gate insulator;
a second gate insulator formed on the first floating gate and serving as an F-N tunneling film;
a second floating gate formed on the second gate insulator;
an intergate insulator formed on the second floating gate and serving as a charge blocking film; and
a control gate formed on the intergate insulator,
wherein
at least one of the first and second floating gates includes a metal layer, and
a work function of material forming a lower surface of the second floating gate is higher than a work function of material forming an upper surface of the first floating gate.
2. The device according to claim 1 , wherein
the first floating gate is formed of metal material, and the second floating gate is formed of polysilicon.
3. The device according to claim 1 , wherein
the first floating gate is formed of polysilicon, and the second floating gate is formed of metal material.
4. The device according to claim 3 , wherein
a work function of the metal material forming the second floating gate is higher than a work function of the polysilicon.
5. The device according to claim 3 , wherein
a work function of the metal material forming the second floating gate is higher than 4.1 eV.
6. The device according to claim 1 , wherein
each of the first and second floating gates is formed of metal material.
7. The device according to claim 1 , wherein
the first floating gate includes a plurality of layers, and
an uppermost layer of the first floating gate is formed of metal material.
8. The device according to claim 1 , wherein
the second floating gate includes a plurality of layers, and
a lowermost layer of the second floating gate is formed of metal material.
9. The device according to claim 1 , wherein
each of the first and second floating gates includes a plurality of layers, and
each of an uppermost layer of the first floating gate and a lowermost layer of the second floating gate is formed of metal material.
10. The device according to claim 1 , wherein
the first floating gate is fully or partially silicided.
11. The device according to claim 1 , wherein
the second floating gate is fully or partially silicided.
12. The device according to claim 1 , wherein
a work function of material forming an upper surface of the first floating gate is different from a work function of material forming a lower surface of the first floating gate.
13. The device according to claim 1 , wherein
a work function of material forming an upper surface of the second floating gate is different from a work function of material forming a lower surface of the second floating gate.
14. The device according to claim 1 , wherein
a thickness of the first gate insulator and a thickness of the second gate insulator is equal to or greater than 3 nm in equivalent silicon oxide thickness.
15. The device according to claim 1 , further comprising:
a plurality of bitlines extending in a first direction parallel to a surface of the substrate;
a plurality of wordlines extending in a second direction parallel to the surface of the substrate; and
a plurality of cell transistors, each of which includes the first gate insulator, the first floating gate, the second gate insulator, the second floating gate, the intergate insulator, and the control gate, and is electrically connected to one of the bitlines and one of the wordlines,
wherein the intergate insulator and the control gate are shared by the cell transistors adjacent to one another in a direction parallel to the wordlines.
16. The device according to claim 15 , wherein
a height of a lower surface of the control gate between the cell transistors is lower than a height of a lower surface of the control gate on the first and second floating gates.
17. The device according to claim 15 , wherein
a height of a lower surface of the control gate between the cell transistors is substantially equal to a height of a lower surface of the control gate on the first and second floating gates.