COL package having small chip hidden between leads
A Chip-On-Lead (COL) type semiconductor package having small chip hidden between leads is revealed. The lower surfaces of the leadframe's leads are attached to a wiring substrate and the leads are horizontally bent to form a die-holding cavity. A smaller chip is disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads. At least a larger chip is disposed on the leads to overlap the smaller chip so that the small chip does not extrude from the leads. The encapsulant encapsulates a plurality of internal parts of the leads, the wiring substrate, and the larger chip. Therefore, the conventional unbalance issue of mold flow above and below the leads leading to cause excessive warpage can be avoided and numbers of stacked larger chips can be increased to have larger memory capacities.
1. A Chip-On-Lead (COL) type semiconductor package comprising:
a plurality of leads of a leadframe, wherein the leads are horizontally bent to form a die-holding cavity;
a wiring substrate disposed under the leads;
a first chip disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads;
a second chip disposed on the leads to overlap the first chip;
an encapsulant encapsulating a plurality of internal parts of the leads, the wiring substrate; and the second chip;
a plurality of first bonding wires electrically connecting the wiring substrate to the leads; and
a plurality of second bonding wires electrically connecting the second chip to the leads and to the wiring substrate.
2. The semiconductor package as claimed in claim 1 , further comprising a plurality of third bonding wires electrically connecting the first chip to the wiring substrate.
3. The semiconductor package as claimed in claim 1 , wherein the leads includes a plurality of first side leads and a plurality of second side leads where the first side leads is longer than the second side leads exceeding a central line of the encapsulant and the die-holding cavity is defined by the first side leads.
4. The semiconductor package as claimed in claim 3 , wherein the wiring substrate has a plurality of bonding fingers disposed on a top surface of the wiring substrate and located at a gap between the first side leads and the second side leads.
5. The semiconductor package as claimed in claim 3 , wherein the first side leads are downset relative to the second side leads.
6. The semiconductor package as claimed in claim 1 , wherein the first chip is a controller chip and the second chip is a memory chip, wherein the first chip is smaller than the second chip.
7. The semiconductor package as claimed in claim 6 , further comprising at least a third chip disposed on the second chip having the same dimension as the second chip.
8. The semiconductor package as claimed in claim 7 , wherein the second chip and the third chip are stepwise stacked without overlapping a plurality of bonding pads of the second chip.
9. The semiconductor package as claimed in claim 1 , wherein the wiring substrate has a bottom surface exposed from the bottom of the encapsulant and a plurality of external connecting pads disposed on the bottom surface.
10. The semiconductor package as claimed in claim 9 , further comprising a plurality of solder balls jointed to the external connecting pads.
11. The semiconductor package as claimed in claim 1 , further comprising a die-attaching material adhering the second chip to the leads and encapsulating the first chip.
12. The semiconductor package as claimed in claim 11 , wherein the die-attaching material includes an underfilling material.
13. The semiconductor package as claimed in claim 1 , wherein the thickness of the first chip is not greater than the thickness of the leads.
14. A Chip-On-Lead (COL) type semiconductor package comprising:
a plurality of leads of a leadframe, wherein the leads are horizontally bent to form a die-holding cavity;
a wiring substrate disposed under the leads;
a first chip disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads;
a second chip disposed on the leads to overlap the first chip; and
an encapsulant encapsulating a plurality of internal parts of the leads, the wiring substrate, and the second chip;
wherein the leads includes a plurality of first side leads and a plurality of second side leads where the first side leads is longer than the second side leads exceeding a central line of the encapsulant and the die-holding cavity is defined by the first side leads.
15. The semiconductor package as claimed in claim 14 , wherein the wiring substrate has a plurality of bonding fingers disposed on a top surface of the wiring substrate and located at a gap between the first side leads and the second side leads.
16. The semiconductor package as claimed in claim 14 , wherein the first side leads are downset relative to the second side leads.
17. A Chip-On-Lead (COL) type semiconductor package comprising:
a plurality of leads of a leadframe, wherein the leads are horizontally bent to form a die-holding cavity;
a wiring substrate disposed under the leads;
a first chip disposed on the wiring substrate by passing through the die-holding cavity to be on the same disposing level with the leads;
a second chip disposed on the leads to overlap the first chip;
a die-attaching material adhering the second chip to the leads and encapsulating the first chip, wherein the die-attaching material includes an underfilling material; and
an encapsulant encapsulating a plurality of internal parts of the leads, the wiring substrate, and the second chip.
18. The semiconductor package as claimed in claim 17 , wherein the wiring substrate has a bottom surface exposed from the bottom of the encapsulant and a plurality of external connecting pads disposed on the bottom surface.
19. The semiconductor package as claimed in claim 18 , further comprising a plurality of solder balls jointed to the external connecting pads.
20. The semiconductor package as claimed in claim 17 , wherein the first chip is a controller chip and the second chip is a memory chip, wherein the first chip is smaller than the second chip, the semiconductor package further comprising at least a third chip disposed on the second chip having the same dimension as the second chip.