System for protecting supervisor mode data from user code
View Patent ↗A system for protecting supervisor mode data from user code having a processor which implements a register window architecture supporting as separate window stacks for supervisor and user modes with a transition window in one of the window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, supervisor mode-only memory storing the supervisor mode window stack, and user mode accessible memory storing the supervisor and user mode window stacks.
1. A system for protecting supervisor mode data from user code, the system comprising: a processor which implements a register window architecture having separate register window stacks for supervisor and user modes with a transition window in one of the register window stacks set with at least one invalid window bit in an invalid window mask of the architecture additional to an invalid window bit set for a reserved window of the invalid window mask for transitioning from the supervisor mode to the user mode, wherein a unique numerical label is assigned to each register window of the register window stacks starting from 0 and increasing monotonically for every save, the assigned labels being inaccessible to user code and being used to access the invalid window bits of the register windows.
2. A system according to claim 1 , wherein processor maintains the position of the additional invalid window bit in the invalid window mask independent of window overflows and underflows at the transition window.
3. A system according to claim 1 , wherein:
the processor switches a current stack pointer to the supervisor stack whenever a transition from user mode to supervisor mode occurs; and
the processor switches the current stack pointer to the user stack whenever a transition from supervisor mode to user mode occurs.
4. A system according to claim 1 , wherein the processor records information on the transition window in the supervisor stack upon window overflow and underflow at the transition window.
5. A system according to claim 1 , wherein the processor records information on non-transition windows in the supervisor stack upon window overflow and underflow at the non-transition windows.
6. A system according to claim 1 , wherein registers in the transition window are overwritten upon window overflow and underflow at the transition window.