IP Library Granted Patent US 8,084,279
Granted Patent B2
US 8,084,279 · App. 12/720,248 · Granted Dec 27, 2011

Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,084,279
App. No.
12/720,248
Granted
Dec 27, 2011
Kind
B2
Abstract

According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. A step of preparing a phase shift mask and a normal photomask. A step of stacking a first wiring layer on a semiconductor substrate, and further stacking, on the first wiring layer, a second wiring layer. The second wiring layer includes a second wiring and third wiring. A step of stacking an interlayer insulating film on the second wiring layer. A step of forming, in the interlayer insulating film, a first opening in which the second wiring is exposed, and a second opening in which the third wiring is exposed by photolithography using the normal photomask. A step of burying a metal in the first opening and the second opening. A step of providing a pad to be overlaid on the first and second openings.

Claims (14)

1. A method of manufacturing a semiconductor device, comprising the steps of:

stacking a first wiring layer on a semiconductor substrate;

stacking, on the first wiring layer, a second wiring layer constituted by including a second wiring which is connected to a wiring of said first wiring layer, and a third wiring which is not connected to the wiring of the first wiring layer;

stacking an interlayer insulating film on said second wiring layer;

forming, in a certain region of said interlayer insulating film, a first opening in which said second wiring is exposed, and a second opening in which said third wiring is exposed;

burying a metal in said first opening and said second opening;

providing a pad extending through the certain region to a region outside the certain region, on said interlayer insulating film,

performing probing into a portion on said certain region, which is a surface of said pad; and

connecting a wiring for external connection to a portion on the region outside said certain region, which is a surface of said pad.

2. The method of manufacturing a semiconductor device according to claim 1 ,

wherein said step of stacking said second wiring layer includes a step of forming a fourth wiring connected to the wiring of said first wiring layer, in a region different from said second wiring and said third wiring, and

said step of providing the pad is a step of forming said pad to extend to a position of an upper layer of said fourth wiring.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein said fourth wiring is a wiring constituting a level shift circuit.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein said step of probing into said pad includes a step of probing a cantilever type probe formed of a material including tungsten into the pad.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Sep 13, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024973/0598 →