IP Library › Granted Patent US 8,048,759
Granted Patent B2
US 8,048,759 · App. 12/720,287 · Granted Nov 1, 2011

Semiconductor device and method of manufacturing the same

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,048,759
App. No.
12/720,287
Granted
Nov 1, 2011
Kind
B2
Abstract

The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.

Claims (14)

1. A method of manufacturing a semiconductor device to an SOI substrate in which an insulating layer and a silicon layer are laminated over a silicon substrate, comprising: a FIN type first active element in which a first control electrode coils around a body region formed in the silicon layer; and a planar type second active element which is separated using partial isolation and full isolation together to element isolation, and is formed in the silicon layer; and comprising the steps of:

doing element isolation formation which forms in a predetermined position of the silicon layer a full isolation film which reaches in the insulating layer, and a partial isolation film which does not reach in the insulating layer;

removing the full isolation film in a predetermined position where the first active element is formed; and

doing control electrode formation which forms a second control electrode of the second active element at the same time of forming the first control electrode in a position where the full isolation film is removed in the removing step.

2. A method of manufacturing a semiconductor device according to claim 1 , wherein

in the step of doing the element isolation formation, nitriding treatment is performed, before forming the full isolation film and the partial isolation film.

3. A method of manufacturing a semiconductor device according to claim 1 , wherein

in the step of doing the element isolation formation, nitrogen implantation is performed to the insulating layer which forms the full isolation film.

4. A method of manufacturing a semiconductor device according to claim 1 , wherein

in the step of doing the element isolation formation, after forming the partial isolation film, the full isolation film is formed.

5. A method of manufacturing a semiconductor device according to claim 1 , wherein

in the step of doing the control electrode formation, simultaneously with formation of the first control electrode, a spacer electrically connected with the first control electrode is formed at a side wall of the body region.

6. A method of manufacturing a semiconductor device according to claim 1 , further comprising a step of:

siliciding the first control electrode and the second control electrode, and the silicon layer of a predetermined region.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Sep 1, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024915/0526 →
MERGER Recorded Sep 1, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024915/0556 →
Priority Claims (1)
JP 2006-285688 · Oct 20, 2006 · national
Continuity (2)
Division 11870610 · Oct 11, 2007
Related Publication 20100167492A1 · Jul 1, 2010