SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a plurality of transistors on a semiconductor substrate; a first interlayer dielectric film on the transistors; a plurality of ferroelectric capacitors on the first interlayer dielectric film; a first hydrogen barrier film covering an upper surface and a side surface of each of the ferroelectric capacitors; a second interlayer dielectric film above the ferroelectric capacitors, the second interlayer dielectric film being buried to have a void or hole between two adjacent ferroelectric capacitors out of the ferroelectric capacitors; a cover dielectric film covering the second interlayer dielectric film to close an opening of the void or hole; and a second hydrogen barrier film covering the cover dielectric film.
1 . A semiconductor memory device comprising:
a plurality of transistors on a semiconductor substrate;
a first interlayer dielectric film on the transistors;
a plurality of ferroelectric capacitors on the first interlayer dielectric film;
a first hydrogen barrier film on an upper surface and a side surface of each ferroelectric capacitor;
a second interlayer dielectric film above the ferroelectric capacitors and inbetween two adjacent ferroelectric capacitors out of the ferroelectric capacitors with either a gap or a hole;
a cover dielectric film on the second interlayer dielectric film configured to close an opening of the gap or hole; and
a second hydrogen barrier film on the cover dielectric film.
2 . The device of claim 1 , wherein a cavity of the gap or hole remains between the two adjacent ferroelectric capacitors.
3 . The device of claim 1 , wherein the cover dielectric film is in the gap or hole and configured to cover the second interlayer dielectric film.
4 . The device of claim 1 , wherein the cover dielectric film comprises a material of the second interlayer dielectric film.
5 . The device of claim 2 , wherein the cover dielectric film comprises a material of the second interlayer dielectric film.
6 . The device of claim 3 , wherein the cover dielectric film comprises a material of the second interlayer dielectric film.
7 . The device of claim 1 , wherein the cover dielectric film is thicker than the second hydrogen barrier film.
8 . The device of claim 2 , wherein the cover dielectric film is thicker than the second hydrogen barrier film.
9 . The device of claim 3 , wherein the cover dielectric film is thicker than the second hydrogen barrier film.
10 . The device of claim 1 , wherein a first etching rate for etching the cover dielectric film is higher than a second etching rate for etching the second hydrogen barrier film.
11 . The device of claim 2 , wherein a first etching rate for etching the cover dielectric film is higher than a second etching rate for etching the second hydrogen barrier film.
12 . The device of claim 3 , wherein a first etching rate for etching the cover dielectric film is higher than a second etching rate for etching the second hydrogen barrier film.
13 . The device of claim 1 , wherein an upper surface of the second interlayer dielectric film is flat.
14 . A semiconductor memory device comprising:
a plurality of transistors on a semiconductor substrate;
a first interlayer dielectric film on the transistors;
a plurality of ferroelectric capacitors on the first interlayer dielectric film;
a first hydrogen barrier film on an upper surface and a side surface of each ferroelectric capacitor;
a second interlayer dielectric film above the ferroelectric capacitors and inbetween two adjacent ferroelectric capacitors out of the ferroelectric capacitors with either a gap or hole; and
a second hydrogen barrier film in the gap or hole, and on the second interlayer dielectric film.
15 . The device of claim 14 , wherein an upper surface of the second interlayer dielectric film is flat.
16 . A semiconductor memory device comprising:
a plurality of transistors on a semiconductor substrate;
a first interlayer dielectric film on the transistors;
a plurality of ferroelectric capacitors on the first interlayer dielectric film;
a first hydrogen barrier film on an upper surface and a side surface of each ferroelectric capacitor;
a second interlayer dielectric film above the ferroelectric capacitors and inbetween two adjacent ferroelectric capacitors out of the ferroelectric capacitors; and
a second hydrogen barrier film on the second interlayer dielectric film
wherein the side surface of each of the ferroelectric capacitors is in a forward tapered shape with an angle equal to or smaller than 70 degrees with respect to a bottom or the upper surface of each ferroelectric capacitor.