Method of dual EPI process for semiconductor device

1. A method of fabricating a semiconductor device, comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material that is doped;

forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material, wherein the second material is undoped;

forming a protection layer over the second region to protect the second gate structure;

removing the capping layer over the first gate structure;

removing the protection layer over the second region;

epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region; and

removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material that is undoped to the first material that is doped,

wherein removing the capping layer over the second gate structure by the etching process that exhibits the etching selectivity of the second material that is undoped to the first material that is doped occurs prior to forming another capping layer over the second gate structure, the another capping layer being formed of the second material.

2. The method of claim 1 , wherein the first material comprises silicon nitride doped with carbon.

3. The method of claim 2 , wherein the second material comprises silicon nitride not doped with carbon.

4. The method of claim 1 , further comprising:

prior to forming the capping layer over the first and second gate structures, forming an oxide layer over the first and second gate structures;

prior to removing the protection layer over the second region, removing the oxide layer over the first gate structure; and

after epi growing the semiconductor material, removing the oxide layer over the second gate structure by wet etching, wherein the wet etching selectively etches the oxide layer but not the first material of the spacers disposed on the sidewalls of the first gate structure.

5. The method of claim 1 , wherein the epi growing the semiconductor material forms raised source and drain features at either side of the first gate structure.

6. The method of claim 1 , further comprising thereafter:

forming another capping layer over the first and second gate structures, the another capping layer being formed of the second material;

forming another protection layer over the first region to protect the first gate structure;

removing the another capping layer over the second gate structure;

etching a recess in the substrate at either side of the second gate structure, the recess having sides aligned with the spacers disposed on the sidewalls of the second gate structure;

removing the another protection layer over the first region;

epitaxially growing another semiconductor material to fill the recess; and

removing the another capping layer over the first gate structure by the etching process that exhibits the etching selectivity of the second material layer to the first material.

7. The method of claim 6 , further comprising:

prior to forming the another capping layer over the first and second gate structures, forming an oxide layer over the first and second gate structures;

prior to removing the another protection layer over the first region, removing the oxide layer over the second gate structure; and

after epi growing the another semiconductor material, removing the oxide layer over the first gate structure by wet etching, wherein the wet etching selectively etches the oxide layer but not the first material of the spacers disposed on the sidewalls of the second gate structure.

8. The method of claim 6 , wherein the semiconductor material includes silicon (Si) and wherein the another semiconductor material includes silicon germanium (SiGe).

9. The method of claim 6 , wherein the first gate structure is part of an NMOS device and wherein the second gate structure is part of a PMOS device.

10. The method of claim 1 , further comprising etching a recess in the substrate adjacent the second gate structure; and

epitaxially growing another semiconductor material to fill the recess.

11. A method comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a first material;

forming a capping layer over the first and second gate structures, the capping layer being formed of a second material different from the first material;

forming a protection layer over the second region to protect the second gate structure;

removing the capping layer over the first gate structure;

removing the protection layer over the second region;

epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region;

removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the second material to the first material,

after removing the capping layer, forming another capping layer over the first and second gate structures, the another capping layer being formed of the second material;

removing the another capping layer over the second gate structure; and

epitaxially (epi) growing another semiconductor material on exposed portions of the substrate in the second region.

12. The method of claim 11 , further comprising removing the another capping layer over the first gate structure by the etching process that exhibits the etching selectivity of the second material layer to the first material.

13. The method of claim 11 , wherein epitaxially (epi) growing the second semiconductor material on exposed portions of the substrate in the second region includes:

etching a recess in the substrate at either side of the second gate structure; and

epitaxially growing another semiconductor material to fill the recess.

14. The method of claim 13 , wherein the recess having sides aligned with the spacers disposed on the sidewalls of the second gate structure.

15. The method of claim 11 , further comprising forming another protection layer over the another capping layer in the first region prior to removing the another capping layer over the second gate structure.

16. The method of claim 15 , removing the protection layer over the first gate structure prior to epitaxially (epi) growing another semiconductor material on exposed portions of the substrate in the second region.

17. A method comprising:

forming first and second gate structures over first and second regions of a substrate, respectively;

forming spacers on sidewalls of the first and second gate structures, the spacers being formed of a doped first material;

forming a capping layer over the first and second gate structures, the capping layer being formed of a undoped second material;

forming a protection layer over the second region to protect the second gate structure;

removing the capping layer over the first gate structure;

removing the protection layer over the second region;

epitaxially (epi) growing a semiconductor material on exposed portions of the substrate in the first region;

removing the capping layer over the second gate structure by an etching process that exhibits an etching selectivity of the undoped second material to the doped first material;

after removing the capping layer, forming another capping layer over the first and second gate structures, the another capping layer being formed of the second material;

removing the capping layer over the second gate structure; and

epitaxially (epi) growing another semiconductor material on exposed portions of the substrate in the second region.

18. The method of claim 17 , further comprising forming first and second fins in the first and second regions of the substrate, respectively.

19. The method of claim 17 , wherein the undoped second material of the capping layer includes a silicon nitride layer disposed over the silicon oxide layer; and

wherein the doped first material of the spacers includes silicon nitride doped with carbon.

20. The method of claim 17 , wherein forming spacers on sidewalls of the first and second gate structures includes forming performing an etching process to form the spacers, and

wherein forming the capping layer over the first and second gate structures occurs after performing the etching process to form the spacers.