Epitaxial methods for reducing surface dislocation density in semiconductor materials
View Patent ↗The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor layer having a primary semiconductor surface comprising a plurality of surface pits associated with emergent dislocations;
masking a plurality of the emergent dislocations with caps fabricated from a first masking layer, each cap extending at least partially into a surface pit of the plurality of surface pits;
removing a portion of the semiconductor layer to form a secondary semiconductor surface;
forming a plurality of spacer structures adjacent to the caps from a second masking layer, the caps and spacer structures together forming a plurality of dislocation pit plugs; and
growing a following semiconductor layer from the secondary semiconductor surface over the plurality of dislocation pit plugs and producing a substantially continuous following semiconductor layer with fewer dislocations than the provided semiconductor layer.
2. The method of claim 1 , wherein the plurality of surface pits of the primary semiconductor surface are produced by etching the primary semiconductor surface under etch conditions that encourage etching at or proximate to the emergent dislocations and that discourages etching away from the emergent dislocations.
3. The method of claim 1 , wherein the plurality of surface pits of the primary semiconductor surface are produced by:
etching an initial semiconductor surface under etch conditions that encourage etching at or proximate to the emergent dislocations and that discourages etching away from the emergent dislocations; and
growing a semiconductor layer on the initial semiconductor surface under epitaxial growth conditions that are selected to encourage opening of the surface pits and the agglomeration of two or more surface pits at the primary surface.
4. The method of claim 1 , wherein masking a plurality of the surface pits with caps further comprises:
depositing one or more amorphous materials on the primary semiconductor surface; and
removing portions of the amorphous materials deposited on the primary semiconductor surface which are not masking the surface pits.
5. The method of claim 4 , wherein removing portions of the amorphous materials is performed by at least one of chemical mechanical polishing and plasma etching.
6. The method of claim 1 , wherein removing a portion of the semiconductor layer is performed by plasma etching with chlorine-based etch chemistries.
7. The method of claim 1 , wherein forming a plurality of spacer structures further comprises:
depositing one or more substantially conformal amorphous materials; and
anisotropically etching the one or more substantially conformal amorphous materials until the portions of the secondary semiconductor surface away from the dislocation pit plugs are exposed.
8. The method of claim 1 , wherein the provided semiconductor layer and the following semiconductor layer each comprise III-nitride material.
9. The method of claim 1 , wherein the first and second masking layers each comprise silicon oxides, silicon nitrides or a mixture thereof.
10. The method of claim 1 , further comprising increasing a volume of at least one of the plurality of surface pits.
11. The method of claim 10 , wherein increasing a volume of at least one of the plurality of surface pits comprises exposing the primary semiconductor surface to an etch chemistry comprising at least one of a halogen, potassium hydroxide, sodium hydroxide, and phosphoric acid.
12. The method of claim 1 , wherein masking a plurality of the emergent dislocations with caps fabricated from a first masking layer comprises providing an initial masking material on the primary semiconductor surface and providing a subsequent material on the initial masking material.
13. The method of claim 1 , wherein forming a plurality of spacer structures further comprises:
depositing the second masking layer substantially conformally over the secondary semiconductor surface and the caps; and
removing a portion of the second masking layer from the secondary semiconductor surface, leaving another portion of the second masking layer encircling the caps.
14. The method of claim 1 , wherein growing a following semiconductor layer comprises growing the following semiconductor layer having a thickness less than approximately 1000 μm.
15. The method of claim 14 , wherein growing a following semiconductor layer comprises growing the following semiconductor layer having a thickness less than approximately 100 μm.
16. The method of claim 15 , wherein growing a following semiconductor layer comprises growing the following semiconductor layer having a thickness less than approximately 1 μm.
17. A method of forming a semiconductor structure, comprising:
providing a first semiconductor layer comprising gallium nitride over a sapphire base substrate, the first semiconductor layer having a primary surface comprising a plurality of surface pits associated with emergent dislocations;
masking a plurality of the emergent dislocations with caps fabricated from a first masking layer, each cap extending at least partially into a surface pit of the plurality of surface pits;
removing a portion of the first semiconductor layer to form a secondary surface;
forming a plurality of spacer structures adjacent to the caps from a second masking layer, the caps and spacer structures together forming a plurality of dislocation pit plugs; and
growing a second semiconductor layer from the secondary surface over the plurality of dislocation pit plugs, second semiconductor layer comprising gallium nitride and having fewer dislocations than the first layer.
18. The method of claim 17 , further comprising exposing the first semiconductor layer to a mixture of silane, ammonia, and hydrogen to increase a volume of at least one of the plurality of surface pits.
19. The method of claim 17 , wherein masking a plurality of the emergent dislocations with caps fabricated from a first masking layer further comprises removing a portion of the first masking layer by chemical mechanical polishing.
20. The method of claim 17 , wherein removing a portion of the first semiconductor layer to form a secondary surface comprises etching the first semiconductor layer by a reactive ion etching process utilizing a chlorine gas chemistry.