Method for fabricating a shielded gate trench MOS with improved source pickup layout
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
1. A method for fabricating a semiconductor device, comprising:
a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches;
a′) forming asymmetric sidewalls in the gate runner/termination trenches, wherein forming asymmetric sidewalls includes undercut etching a portion of an oxide layer that is at least in part covered due to application of the second mask;
b) forming a first conductive region in the plurality of trenches;
c) forming an intermediate dielectric region and a termination protection region by applying a second mask;
d) forming a second conductive region in at least some of the trenches;
e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask;
f) disposing a metal layer; and
g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.
2. The method of claim 1 , wherein the asymmetric sidewalls includes a first sidewall and a second sidewall, and the first sidewall has a thicker oxide layer than the second sidewall, the first sidewall being closer to the termination area.
3. A method for fabricating a semiconductor device, comprising:
a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches;
b) forming a first conductive region in the plurality of trenches;
c) forming an intermediate dielectric region and a termination protection region by applying a second mask, wherein during formation of the intermediate dielectric region and the termination protection region, the second mask covers the gate runner/termination trenches and the source pickup trenches;
d) forming a second conductive region in at least some of the trenches;
e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask;
f) disposing a metal layer; and
g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.
4. The method of claim 3 , wherein the gate runner/termination trenches are wider than the active gate trenches and the source pickup trenches.
5. A method for fabricating a semiconductor device, comprising:
a) forming a plurality of trenches by applying a first mask, the plurality of trenches include active gate trenches located in an active area, gate runner/termination trenches and source pickup trenches located in a termination area outside an active area containing the active gate trenches,
a′) forming a plurality of trench spacers around openings of the plurality of trenches, wherein said trench spacers protect a semiconductor mesa area for forming a self-aligned cell contact;
b) forming a first conductive region in the plurality of trenches;
c) forming an intermediate dielectric region and a termination protection region by applying a second mask;
d) forming a second conductive region in at least some of the trenches, wherein said trench spacers help protect a semiconductor surface while forming a polycide on the second conductive region;
e) forming a first electrical contact to the second conductive regions and forming a second electrical contact to the first conductive region in the source pickup trenches located in the termination area by applying a third mask;
f) disposing a metal layer; and
g) forming a source metal region and a gate metal region from the metal layer by applying a fourth mask.
6. The method of claim 1 , wherein the source pickup trenches are located in between adjacent active areas.
7. The method of claim 6 , wherein the source pickup trench is surrounded by gate runner/termination trenches.
8. The method of claim 1 , further comprising forming asymmetric sidewalls in the gate runner/termination trenches.
9. The method of claim 1 , wherein forming an intermediate dielectric region completely fills the active gate trench, but does not completely fill the gate runner/termination trench or gate pickup trench.
10. The method of claim 1 , wherein b) includes partially filling the trenches with a conductive material by a first deposition process, partially etching the conductive material, and filling an unfilled portion of the trenches by a second deposition process.
11. The method of claim 10 wherein the plurality of trenches includes one or more high aspect ratio trenches characterized by an aspect ratio of about 10:1 or greater.
12. The method of claim 3 , wherein the source pickup trenches are located in between adjacent active areas.
13. The method of claim 12 , wherein the source pickup trench is surrounded by gate runner/termination trenches.
14. The method of claim 3 , further comprising forming asymmetric sidewalls in the gate runner/termination trenches.
15. The method of claim 3 , wherein forming an intermediate dielectric region completely fills the active gate trench, but does not completely fill the gate runner/termination trench or gate pickup trench.
16. The method of claim 3 , wherein b) includes partially filling the trenches with a conductive material by a first deposition process, partially etching the conductive material, and filling an unfilled portion of the trenches by a second deposition process.
17. The method of claim 16 wherein the plurality of trenches includes one or more high aspect ratio trenches characterized by an aspect ratio of about 10:1 or greater.
18. The method of claim 5 , wherein the source pickup trenches are located in between adjacent active areas.
19. The method of claim 18 , wherein the source pickup trench is surrounded by gate runner/termination trenches.
20. The method of claim 5 , further comprising forming asymmetric sidewalls in the gate runner/termination trenches.
21. The method of claim 5 , wherein forming an intermediate dielectric region completely fills the active gate trench, but does not completely fill the gate runner/termination trench or gate pickup trench.
22. The method of claim 5 , wherein b) includes partially filling the trenches with a conductive material by a first deposition process, partially etching the conductive material, and filling an unfilled portion of the trenches by a second deposition process.
23. The method of claim 22 wherein the plurality of trenches includes one or more high aspect ratio trenches characterized by an aspect ratio of about 10:1 or greater.