IP Library Granted Patent US 8,093,143
Granted Patent B2
US 8,093,143 · App. 12/724,584 · Granted Jan 10, 2012

Method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side

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Quick Facts
Patent No.
US 8,093,143
App. No.
12/724,584
Granted
Jan 10, 2012
Kind
B2
Abstract

A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

Claims (11)

1. A method for producing a wafer comprising a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method comprising steps in the following order:

simultaneously polishing the front and the back side of the silicon single crystal substrate;

depositing a stress compensating layer on the back side of the silicon single crystal substrate;

polishing the front side of the silicon single crystal substrate;

cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and

depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

2. The method of claim 1 , further comprising: depositing a silicon cap layer on the stress compensating layer.

3. The method of claim 1 , further comprising: polishing an edge and a notch of the wafer comprising the silicon single crystal substrate with the stress compensating layer deposited on the back side and the heteroepitaxial layer of SiGe deposited on the front side of the silicon single crystal substrate.

4. The method of claim 1 , further comprising: polishing and cleaning the heteroepitaxial layer of SiGe deposited on the front side of the silicon single crystal substrate.

5. The method of claim 1 , further comprising: depositing one or more further epitaxial layers on the SiGe layer deposited on the front side of the silicon single crystal substrate.

6. The method of claim 5 , comprising polishing the front side of the wafer before depositing a further epitaxial layer, wherein polishing is performed as chemical mechanical polishing in the presence of a slurry containing abrasive particles or as fixed abrasive polishing in the absence of a slurry containing abrasive particles.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2010
From: STORCK, PETER; BUSCHHARDT, THOMAS
To: SILTRONIC AG
Reel/Frame 024086/0168 →