METHOD OF SEMICONDUCTOR CIRCUIT DEVICE

1 . A designing method of a semiconductor circuit device comprising:

generating a circuit diagram data indicating a semiconductor circuit device which includes a plurality of power source separation regions, each of said plurality of power source separation regions being provided with a plurality of cells which includes a plurality of retention flip-flops;

generating a net list indicating wiring lines between said plurality of power source separation regions and nodes connected thereof, based on said circuit diagram data;

when an output of a first power source separation region of said plurality of power source separation regions is connected to an input of a second power source separation region of said plurality of power source separation regions, and a first power source supplied to said first power source separation region is turned off, searching a first searched cell indicating a retention flip-flop closest to said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

searching a second searched cell between said first searched cell and said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

replacing a power source supplied to an output of said first searched cell from said first power source to a second power source which supplies the same voltage as that of said first power source and is in an on-state all the time; and

replacing a power source supplied to said second searched cell from said first power source to said second power source.

2 . The designing method of a semiconductor circuit device according to claim 1 , wherein said net list includes a first instance name of said first searched cell, a first cell name of said first searched cell, a second instance name of said second searched cell and a second cell name of said second searched cell,

wherein said designing method of a semiconductor circuit device, further comprising:

generating a retention flip-flop replacement list correlating said first instance name and said first cell name with a third cell name of a power-off state output determinate cell which indicates that a power source supplied to said output of said first searched cell is said second power source; and

generating a normally ON cell replacement list correlating said second instance name and said second cell name with a fourth cell name of a normally ON cell which indicates that a power source supplied to said second searched cell is said second power source,

wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, includes:

generating said power-off state output determinate cell by connecting said output of said first searched cell to said second power source based on said retention flip-flop replacement list to determine an output signal from said output, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, includes:

generating said normally ON cell by connecting said second searched cell to said second power source based on said normally ON cell replacement list.

3 . The designing method of a semiconductor circuit device according to claim 2 , wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, further includes:

replacing said, first cell name included in said net list by said third cell name based on said retention flip-flop replacement list, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, further includes:

replacing said second cell name included in said net list by said fourth cell name based on said normally ON cell replacement list.

4 . The designing method of a semiconductor circuit device according to claim 1 , wherein said retention flip-flop closest as said first searched cell includes:

an input circuit inputting data,

a holding circuit holding said data, and

an output circuit outputting said data based on a clock signal,

wherein said input circuit and said output circuit are connected to said first power source, and said holding circuit is connected to said second power source, and

wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, includes:

connecting said output circuit to said second power source.

5 . The designing method of a semiconductor circuit device according to claim 1 , wherein said second searched cell includes a plurality of circuits,

wherein said plurality of circuits is connected to said first power source, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, includes:

connecting said plurality of circuits to said second power source.

6 . The designing method of a semiconductor circuit device according to claim 1 , further comprising:

calculating a leak current value which increases when said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, as a first leak current value by simulation;

calculating a leak current value which increases when said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, as a second leak current value by simulation; and

providing an indeterminate propagation preventing circuit between said output of said first power source separation region and said input of said second power source separation region when at least one of said first leak current value and said second leak current value is equal to or larger than a preset leak current tolerance, said indeterminate propagation preventing circuit preventing an indeterminate signal from propagating from said first power source separation region to said second power source separation region when said first power source supplied to said first power source separation region is in a power-off state.

7 . A computer-readable medium including a computer program comprising code operable to control a computer for a designing method of a semiconductor circuit device, the code comprising;

generating a circuit diagram data indicating a semiconductor circuit device which includes a plurality of power source separation regions, each of said plurality of power source separation regions being provided with a plurality of cells which includes a plurality of retention flip-flops;

generating a net list indicating wiring lines between said plurality of power source separation regions and nodes connected thereof, based on said circuit diagram data;

when an output of a first power source separation region of said plurality of power source separation regions is connected to an input of a second power source separation region of said plurality of power source separation regions, and a first power source supplied to said first power source separation region is turned off, searching a first searched cell indicating a retention flip-flop closest to said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

searching a second searched cell between said first searched cell and said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

replacing a power source supplied to an output of said first searched cell from said first power source to a second power source which supplies the same voltage as that of said first power source and is in an on-state all the time; and

replacing a power source supplied to said second searched cell from said first power source to said second power source.

8 . The computer-readable medium according to claim 7 , wherein said net list includes a first instance name of said first searched cell, a first cell name of said first searched cell, a second instance name of said second searched cell and a second cell name of said second searched cell,

wherein said designing method of a semiconductor circuit device, further comprising:

generating a retention flip-flop replacement list correlating said first instance name and said first cell name with a third cell name of a power-off state output determinate cell which indicates that a power source supplied to said output of said first searched cell is said second power source; and

generating a normally ON cell replacement list correlating said second instance name and said second cell name with a fourth cell name of a normally ON cell which indicates that a power source supplied to said second searched cell is said second power source,

wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, includes:

generating said power-off state output determinate cell by connecting said output of said first searched cell to said second power source based on said retention flip-flop replacement list determine an output signal from said output, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, includes:

generating said normally ON cell by connecting said second searched cell to said second power source based on said normally ON cell replacement list.

9 . The computer-readable medium according to claim 8 , wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, further includes:

replacing said first cell name included in said net list by said third cell name based on said retention flip-flop replacement list, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, further includes:

replacing said second cell name included in said net list by said fourth cell name based on said normally ON cell replacement list.

10 . The computer-readable medium according to claim 7 , wherein said retention flip-flop closest as said first searched cell includes:

an input circuit inputting data a holding circuit holding said data, and

an output circuit outputting said data based on a clock signal,

wherein said input circuit and said output circuit are connected to said first power source, and said holding circuit is connected to said second power source, and

wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, includes:

connecting said output circuit to said second power source.

11 . The computer-readable medium according to claim 7 , wherein said second searched cell includes a plurality of circuits,

wherein said plurality of circuits is connected to said first power source, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, includes:

connecting said plurality of circuits to said second power source.

12 . The computer-readable medium according to claim 7 , further comprising:

calculating a leak current value which increases when said step of replacing a power source supplied to said output of said first searched cell from said first power source, to said second power source, as a first leak current value by simulation;

calculating a leak current value which increases when said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, as a second leak current value by simulation; and

providing an indeterminate propagation preventing circuit between said output of said first power source separation region and said input of said second power source separation region when at least one of said first leak current value and said second leak current value is equal to or larger than a preset leak current tolerance, said indeterminate propagation preventing circuit preventing an indeterminate signal from propagating from said first power source separation region to said second power source separation region when said first power source supplied to said first power source separation region is in a power-off state.

13 . A designing system of a semiconductor circuit device comprising:

a circuit diagram data generating portion configured to generate a circuit diagram data indicating a semiconductor circuit device which includes a plurality of power source separation regions, each of said plurality of power source separation regions being provided with a plurality of cells which includes a plurality of retention flip-flops;

a net list generating portion configured to generate a net list indicating wiring lines between said plurality of power source separation regions and nodes connected thereof, based on said circuit diagram data; and

an indeterminate propagation preventing portion,

wherein when an output of a first power source separation region of said plurality of power source separation regions is connected to an input of a second power source separation region of said plurality of power source separation regions, and a first power source supplied to said first power source separation region is turned off, said indeterminate propagation preventing portion:

searches a first searched cell indicating a retention flip-flop closest to said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list,

searches a second searched cell between said first searched cell and said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

replaces a power source supplied to an output of said first searched cell from said first power source to a second power source which supplies the same voltage as that of said first power source and is in an on-state all the time, and

replaces a power source supplied to said second searched cell from said first power source to said second power source.

14 . The designing system of a semiconductor circuit device according to claim 13 , wherein said net list includes a first instance name of said first searched cell, a first cell name of said first searched cell, a second instance name of said second searched cell and a second cell name of said second searched cell,

wherein said indeterminate propagation preventing portion;

generates a retention flip-flop replacement list correlating said first instance name and said first cell name with a third cell name of a power-off state output determinate cell which indicates that a power source supplied to said output of said first searched cell is said second power source; and

generates a normally ON cell replacement list correlating said second instance name and said second cell name with a fourth cell name of a normally ON cell which indicates that a power source supplied to said second searched cell is said second power source,

when replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, generates said power-off state output determinate cell by connecting said output of said first searched cell to said second power source based on said retention flip-flop replacement list to determine an output signal from said output, and

when replacing a power source supplied to said second searched cell from said first power source to said second power source, generates said normally ON cell by connecting said second searched cell to said second power source based on said normally ON cell replacement list.

15 . The designing system of a semiconductor circuit device according to claim 14 , wherein said indeterminate propagation preventing portion:

when replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, replaces said first cell name included in said net list by said third cell name based on said retention flip-flop replacement list, and

when replacing a power source supplied to said second searched cell from said first power source to said second power source, replaces said second cell name included in said net list by said fourth cell name based on said normally ON cell replacement list.

16 . The designing system of a semiconductor circuit device according to claim 13 , wherein said retention flip-flop closest as said first searched cell includes:

an input circuit inputting data,

a holding circuit holding said data, and

an output circuit outputting said data based on a clock signal,

wherein said input circuit and said output circuit are connected to said first power source, and said holding circuit is connected to said second power source, and

wherein said indeterminate propagation preventing portion, when replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, connects said output circuit to said second power source.

17 . The designing system of a semiconductor circuit device according to claim 13 , wherein said second searched cell includes a plurality of circuits,

wherein said plurality of circuits is connected to said first power source, and

wherein said indeterminate propagation preventing portion, when replacing a power source supplied to said second searched cell from said first power source to said second power source, connects said plurality of circuits to said second power source.

18 . The designing system of a semiconductor circuit device according to claim 13 , wherein said indeterminate propagation preventing portion:

calculates a leak current value which increases when said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, as a first leak current value by simulation,

calculates a leak current value which increases when said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, as a second leak current value by simulation, and

provides an indeterminate propagation preventing circuit between said output of said first power source separation region and said input of said second power source separation region when at least one of said first leak current value and said second leak current value is equal to or larger than a preset leak current tolerance, said indeterminate propagation preventing circuit preventing an indeterminate signal from propagating from said first power source separation region to said second power source separation region when said first power source supplied to said first power source separation region is in a power-off state.

19 . A semiconductor circuit device designed by a designing method of a semiconductor circuit device, wherein said designing method comprising:

generating a circuit diagram data indicating a semiconductor circuit device which includes a plurality of power source separation regions, each of said plurality of power source separation regions being provided with a plurality of cells which includes a plurality of retention flip-flops;

generating a net list indicating wiring lines between, said plurality of power source separation regions and nodes connected thereof, based on said circuit diagram data;

when an output of a first power source separation region of said plurality of power source separation regions is connected to an input of a second power source separation region of said plurality of power source separation regions, and a first power source supplied to said first power source separation region is turned off, searching a first searched cell indicating a retention flip-flop closest to said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

searching a second searched cell between said first searched cell and said output of said first power source separation region from said plurality of cells of said first power source separation region, based on said net list;

replacing a power source supplied to an output of said first searched cell from said first power source to a second power source which supplies the same voltage as that of said first power source and is in an on-state all the time; and

replacing a power source supplied to said second searched cell from said first power source to said second power source.

20 . The semiconductor circuit device according to claim 19 , wherein said net list includes a first instance name of said first searched cell, a first cell name, of said first searched cell, a second instance name of said second searched cell and a second cell name of said second searched cell,

wherein said designing method further comprising:

generating a retention flip-flop replacement list correlating said first instance name and said first cell name with a third cell name of a power-off state output determinate cell which indicates that a power source supplied to said output of said first searched cell is said second power source; and

generating a normally ON cell replacement list correlating said second instance name and said second cell name with a fourth cell name of a normally ON cell which indicates that a power source supplied to said second searched cell is said second power source,

wherein said step of replacing a power source supplied to said output of said first searched cell from said first power source to said second power source, includes:

generating said power-off state output determinate cell by connecting said output of said first searched cell to said second power source based on said retention flip-flop replacement list to determine an output signal from said output, and

wherein said step of replacing a power source supplied to said second searched cell from said first power source to said second power source, includes:

generating said normally ON cell by connecting said second searched cell to said second power source based on said normally ON cell replacement list.