Non-volatile memory with erase gate on isolation zones
View Patent ↗The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate ( 16 ), a control gate ( 19 ) and a separate erase gate ( 10 ). The erase gate ( 10 ) is provided in or on isolation zones ( 2 ) provided in the substrate ( 1 ). Because of that, the erase gates ( 10 ) do not add to the cell size. The capacitance between the erase gate ( 10 ) and the floating gate ( 16 ) is small compared with the capacitance between the control gate ( 19 ) and the floating gate ( 16 ), and the charged floating gate ( 16 ) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate ( 10 ) and the floating gate ( 16 ).
1. A method for manufacturing a semiconductor device comprising an erase gate, a floating gate and a control gate, the method comprising:
providing a substrate having a substrate surface with at least two isolation zones having an outer surface away from the substrate,
forming a floating gate extending on the substrate between and at least partially overlapping the two isolation zones,
forming an erase gate on the outer surface of one of said isolation zones, the erase gate configured to provide an electron-flowing discharge between the floating gate and the erase gate, and
forming a control gate over the floating gate.
2. A method according to claim 1 , wherein providing isolation zones in said substrate comprises providing STI zones.
3. A method according to claim 1 , wherein forming a floating gate comprises depositing a conductive layer and etching slits in said conductive layer in order to separate adjacent FGs.
4. A method according to claim 3 , wherein etching said slits is performed such that the slits run over substantially the complete width of the substrate.
5. A method according to claim 3 , the semiconductor device furthermore comprising an access gate, wherein said method furthermore comprises: depositing a dielectric layer on top of the conductive layer, and before forming the control gate, at least partially removing said dielectric layer at a position where the access gate is to be formed.