Semiconductor device including a capacitor electrically connected to a vertical pillar transistor

1. A semiconductor device, comprising:

a first transistor formed in a first region of a substrate, the first transistor having a pillar protruding upwardly from the substrate and an impurity region provided in an upper portion of the pillar;

a second transistor formed in a second region of the substrate;

an insulation interlayer pattern formed on the first region and the second region to cover the second transistor in the second region and expose an upper surface of the pillar in the first region through an opening in the insulation interlayer pattern, wherein an upper surface of the insulation interlayer pattern in the second region is substantially higher than an upper surface of the impurity region in the upper portion of the pillar in the first region; and

a capacitor electrically connected to the impurity region of the first transistor in the first region of the substrate, wherein the capacitor includes a lower electrode which directly contacts the impurity region in the upper portion of the pillar exposed by the insulation interlayer pattern a dielectric layer formed on an entire outer surface of the lower electrode and an upper electrode formed on the dielectric layer,

wherein the upper surface of the insulation interlayer pattern in the second region is substantially higher than a lower surface of the lower electrode of the capacitor.

2. The semiconductor device of claim 1 , wherein an upper surface of the impurity region is substantially coplanar with an upper surface of the substrate in the second region.

3. The semiconductor device of claim 1 , wherein the insulation interlayer pattern has an opening that selectively exposes a portion of the first region where the pillar is formed.

4. The semiconductor device of claim 1 , wherein the first transistor comprises:

the pillar protruding upwardly from the substrate in the first region; a first gate insulation layer formed on a sidewall of the pillar; a first gate electrode formed on the first gate insulation layer; a first impurity region formed under a lower portion of the pillar; and a second impurity region formed in the upper portion of the pillar.

5. The semiconductor device of claim 4 , wherein the pillar is arranged in a first direction and the first gate electrode extends in a second direction different from the first direction.

6. The semiconductor device of claim 4 , further comprising:

a first isolation layer pattern in the first region of the substrate.

7. The semiconductor device of claim 1 , wherein the second transistor comprises:

a second gate insulation layer pattern formed on the substrate in the second region; a second gate electrode formed on the second gate insulation layer pattern; and a third impurity region and a fourth impurity region formed in the substrate of the second region in both sides of the second gate electrode.

8. The semiconductor device of claim 7 , further comprising: a second isolation layer pattern formed in the first region of the substrate.

9. A semiconductor device, comprising:

a semiconductor substrate including a first region and a second region;

a plurality of vertical pillar transistors formed in the first region of the semiconductor substrate, the plurality of vertical pillar transistors each comprising a pillar, a first gate insulation layer provided on a sidewall surface of the pillar, a first gate electrode provided on the first gate insulation layer, an impurity region provided in an upper portion of the pillar which protrudes from the first gate electrode;

a plurality of planar type transistors provided on an upper surface of the substrate in the second region of the substrate; wherein each of the planar type transistors includes a second gate structure having a second gate insulation layer pattern, a second gate electrode, a mask pattern stacked on a surface of the substrate in the second region, and a source/drain under a surface of the substrate in both sides of the second gate structure;

an upper insulation interlayer pattern formed on the first region and the second region in the substrate, wherein the upper insulation layer pattern covers the planar type transistors in the second region and exposes upper surfaces of the pillars in the first region through an opening in the upper insulation interlayer pattern and wherein an upper surface of the upper insulation interlayer pattern in the second region is substantially higher than an upper surface of the impurity region in the upper portion of the pillar in the first region of the substrate;

a first wiring penetrating the upper insulation interlayer pattern and electrically connected to an end portion of the first gate electrode of the vertical pillar transistor,

a second wiring penetrating the upper insulation interlayer pattern and electrically connected to the second gate electrode;

a third wiring penetrating the upper insulation interlayer pattern and electrically connected to the source/drain; and

a capacitor electrically connected to the impurity region of the vertical pillar transistor in the first region of the substrate, wherein the capacitor includes a lower electrode which directly contacts the impurity region in the upper portion of the pillar exposed by the upper insulation interlayer pattern, a dielectric layer formed on substantially an entire outer surface of the lower electrode and an upper electrode formed on the dielectric layer.