Image sensor photodiode arrangement
The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.
1. An image sensor photodiode arrangement comprising:
a photodiode which is defined by a field region in a predetermined shape and formed in an active region;
a floating diffusion region arranged in one side of the photodiode;
a transfer gate which is formed between the photodiode and the floating diffusion region, partially overlapped with the photodiode, and arranged in parallel with the photodiode;
a reset gate arranged in an active region at one side of the floating diffusion region;
a power voltage terminal which is formed in one side of the reset gate and receives a power voltage; and
an active layer which is formed between the power voltage terminal and the photodiode to discharge electrons accumulated on a surface of the photodiode.
2. The image sensor photodiode arrangement according to claim 1 , wherein the active layer has a low*P-type or N-type doping concentration.
3. An image sensor photodiode arrangement comprising:
a photodiode which is defined by a field region in a predetermined shape and formed in an active region;
a floating diffusion region arranged in one side of the photodiode;
a transfer gate which is formed between the photodiode and the floating diffusion region, partially overlapped with the photodiode, and arranged in parallel with the photodiode;
a reset gate arranged in an active region at one side of the floating diffusion region;
a power voltage terminal which is formed in one side of the reset gate and receives a power voltage; and
a muting gate which is formed between the power voltage terminal and the photodiode to discharge electrons accumulated on a surface of the photodiode.
4. The image sensor photodiode arrangement according to claim 3 , wherein the muting gate is constructed to electrically connect the surface of the photodiode and the power voltage terminal to each other when it receives a voltage higher than a threshold level set to 0.4 to 0.6V.
5. An image sensor photodiode arrangement constructed to remove electrons generated from a surface of a photodiode by applying a voltage of a power voltage terminal to a muting gate before an integration time period to electrically connect the surface of the photodiode and a power voltage terminal of an adjacent pixel, wherein when the muting gate is turned off, a threshold voltage is applied to the muting gate to maintain electrical connection between the surface of the photodiode and the power voltage terminal of the adjacent pixel.
6. The image sensor photodiode arrangement according to claim 5 , wherein the photodiode is constructed to supply the voltage of the power voltage terminal when the transfer gate is turned on, and apply the threshold voltage when the transfer gate is turned off.