Clock control circuit and transmitter
A transmitter 1 comprises a clock generation portion 4 , FIFO portion 6 , and serial signal creation portion 7 . The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CK ref , and generates a first clock CK 1 with a high modulation factor and a second clock CK 2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK 1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2 , a parallel data signal which has been synchronized with the first clock CK 1 in the data generation portion 2 and output, and the second clock CK 2 output from the clock generation portion 4 , and synchronizes the parallel data signal P data with the second clock CK 2 and outputs the parallel data signal P data . The serial signal creation portion 7 converts a parallel data signal PR data into a serial data signal S data .
1. A clock control circuit, comprising:
a clock generation portion:
configured to perform spectrum spreading of the frequency of a reference clock to generate:
a first clock with a high modulation factor and
a second clock with a modulation factor lower than the first clock; and
configured to output the generated first clock and second clock, the first clock being output to an external circuit configured to synchronize a parallel data signal with the first clock; and
a FIFO portion:
configured to receive:
the first clock,
the second clock, and
the parallel data signal that is synchronized with the first clock;
configured to synchronize the parallel data signal with the second clock; and
configured to output the resulting parallel data signal.
2. The clock control circuit according to claim 1 , wherein the clock generation portion is arranged at a position closer to the FIFO portion than the external circuit.
3. The clock control circuit according to claim 1 , wherein the clock generation portion comprises:
a first clock generation portion configured to generate the first clock,
a second clock generation portion configured to generate the second clock, and
a phase adjustment circuit:
configured to generate:
a first control signal and
a second control signal to match the phases of the first clock and the second clock;
configured to output the generated first control signal to the first clock generation portion; and
configured to output the generated second control signal to the second clock generation portion.
4. The clock control circuit according to claim 1 , wherein the clock generation portion comprises:
a multiplier circuit:
configured to receive as input the first clock,
configured to multiply the first clock; and
configured to output the resulting first clock.
5. The clock control circuit according to claim 1 wherein the clock generation portion comprises:
a divider circuit:
configured to receive as input the first clock;
configured to divide the frequency of the first clock; and
configured to output the resulting first clock.
6. A transmitter, comprising:
a clock generation portion:
configured to perform spectrum spreading of the frequency of a reference clock to generate:
a first clock with a high modulation factor and
a second clock with a modulation factor lower than the first clock; and
configured to output the generated first clock and second clock, the first clock being output to an external circuit configured to synchronize a parallel data signal with the first clock; and
a FIFO portion:
configured to receive:
the first clock,
the second clock, and
the parallel data signal that is synchronized with the first clock;
configured to synchronize the parallel data signal with the second clock; and
configured to output the resulting parallel data signal; and
a serial transmission signal creation portion:
configured to receive the parallel data signal synchronized with the second clock;
configured to convert the parallel data signal to a serial data signal; and
configured to output the serial data signal.
7. The clock control circuit according to claim 3 , wherein the clock generation portion further comprises:
a multiplier circuit:
configured to receive as input the first clock;
configured to multiply the first clock; and
configured to output the resulting first clock.
8. The clock control circuit according to claim 3 , wherein the clock generation portion further comprises:
a divider circuit:
configured to receive as input the first clock;
configured to divide the frequency of the first clock; and
configured to output the resulting first clock.
9. The clock control circuit according to claim 4 , wherein the clock generation portion further comprises:
a divider circuit:
configured to receive as input the first clock;
configured to divide the frequency of the first clock; and
configured to output the resulting first clock.
10. The clock control circuit according to claim 7 , wherein the clock generation portion further comprises:
a divider circuit:
configured to receive as input the first clock;
configured to divide the frequency of the first clock; and
configured to output the resulting first clock.
11. The clock control circuit according to claim 2 , wherein the clock generation portion comprises:
a first clock generation portion configured to generate the first clock,
a second clock generation portion configured to generate the second clock, and
a phase adjustment circuit:
configured to generate:
a first control signal and
a second control signal to match the phases of the first clock and the second clock;
configured to output the generated first control signal to the first clock generation portion; and
configured to output the generated second control signal to the second clock generation portion.
12. The clock control circuit according to claim 2 , wherein the clock generation portion comprises:
a multiplier circuit:
configured to receive as input the first clock;
configured to multiply the first clock; and
configured to output the resulting first clock.
13. The clock control circuit according to claim 2 , wherein the clock generation portion comprises:
a divider circuit:
configured to receive as input the first clock;
configured to divide the frequency of the first clock; and
configured to output the resulting first clock.
14. A clock control circuit, comprising:
a clock generation portion:
configured to generate:
a first clock with a high modulation factor and
a second clock with a modulation factor lower than the first clock, by spectrum spreading the frequency of a reference clock; and
a FIFO portion:
configured to
receive as inputs:
(i) the first clock from an external circuit that receives the first clock from the clock generation portion,
(ii) a parallel data signal synchronized with the first clock in the external circuit, and
(iii) the second clock output from the clock generation portion; and
configured to synchronize the parallel data signal with the second clock, and
configured to output the resulting parallel data signal.
15. The clock control circuit according to claim 1 , wherein the clock generation portion comprises:
a phase adjustment circuit configured to generate a first control signal and a second control signal to match the phases of the first clock and the second clock, respectively.
16. The clock control circuit according to claim 15 , wherein the first control signal and the second control signal are different.