Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuit

1. A microprocessor integrated circuit, comprising:

first and second processors, wherein the first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor; and

microcode, wherein the second processor is configured to execute the microcode in response to a reset of the second processor, wherein the microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor, wherein the microcode is configured to selectively output the debug information on a first or second external bus based on a flag, wherein the first external bus is an architectural bus of the second processor to which a memory external to the microprocessor integrated circuit is coupled, wherein the second external bus is coupled to the first processor, wherein the second external bus is non-architectural to the second processor and is distinct from the architectural bus of the second processor.

2. The microprocessor integrated circuit of claim 1 , wherein the microcode is configured to read the debug information from an internal memory of the microprocessor integrated circuit to which the first processor stored the debug information prior to the reset.

3. The microprocessor integrated circuit of claim 1 , wherein the microcode is further configured to initialize the second processor, wherein the microcode is configured to output the debug information external to the microprocessor integrated circuit, prior to initializing the second processor, in response to determining that the reset was performed by the first processor.

4. The microprocessor integrated circuit of claim 1 , wherein the microcode is configured to output the debug information on an architectural bus of the second processor to a memory external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor.

5. The microprocessor integrated circuit of claim 1 , wherein the microcode is configured to output the debug information on an external bus coupled to the first processor in response to determining that the reset was performed by the first processor, wherein the external bus is non-architectural to the second processor and is distinct from an architectural bus of the second processor.

6. The microprocessor integrated circuit of claim 1 , wherein the flag is user-programmable.

7. The microprocessor integrated circuit of claim 1 , wherein the debug information comprises information about the state of signals of an architectural bus of the second processor prior to the reset.

8. The microprocessor integrated circuit of claim 7 , wherein the first processor is configured to write the architectural bus signal state information to an internal memory of the microprocessor integrated circuit prior to the reset, wherein the microcode is configured to read the architectural bus signal state information from the internal memory.

9. The microprocessor integrated circuit of claim 1 , wherein the debug information comprises a log of events that occurred with respect to the second processor prior to the reset.

10. The microprocessor integrated circuit of claim 9 , wherein the first processor is configured to write the event log to an internal memory of the microprocessor integrated circuit prior to the reset, wherein the microcode is configured to read the event log from the internal memory.

11. The microprocessor integrated circuit of claim 1 , wherein the debug information comprises information specifying the architectural state of the second processor prior to the reset.

12. A method for debugging a microprocessor integrated circuit comprising first and second processors, the method comprising:

detecting, by the first processor, that the second processor has not retired an instruction for a predetermined amount of clock cycles and responsively resetting the second processor;

executing microcode, by the second processor, in response to a reset of the second processor; and

reading, by the microcode, debug information within the microprocessor integrated circuit and outputting the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor, wherein said outputting the debug information comprises the microcode selectively outputting the debug information on a first or second external bus based on a flag, wherein the first external bus is an architectural bus of the second processor to which a memory external to the microprocessor integrated circuit is coupled, wherein the second external bus is coupled to the first processor, wherein the second external bus is non-architectural to the second processor and is distinct from the architectural bus of the second processor.

13. The method of claim 12 , wherein said reading the debug information comprises reading the debug information from an internal memory of the microprocessor integrated circuit to which the first processor stored the debug information prior to the first processor resetting the second processor.

14. The method of claim 12 , further comprising:

initializing the second processor, by the microcode, wherein the microcode is configured to perform said outputting the debug information prior to initializing the second processor.

15. The method of claim 12 , wherein said outputting the debug information comprises the microcode outputting the debug information on an architectural bus of the second processor to a memory external to the microprocessor integrated circuit.

16. The method of claim 12 , wherein said outputting the debug information comprises the microcode outputting the debug information on an external bus coupled to the first processor, wherein the external bus is non-architectural to the second processor and is distinct from an architectural bus of the second processor.

17. The method of claim 12 , wherein the flag is user-programmable.

18. The method of claim 12 , wherein the debug information comprises information about the state of signals of an architectural bus of the second processor prior to the first processor resetting the second processor.

19. The method of claim 18 , further comprising:

writing, by the first processor, the architectural bus signal state information to an internal memory of the microprocessor integrated circuit prior to the first processor resetting the second processor; and

wherein the microcode reading the architectural bus signal state information comprises the microcode reading the architectural bus signal state information from the internal memory written by the first processor.

20. The method of claim 12 , wherein the debug information comprises a log of events that occurred with respect to the second processor prior to the first processor resetting the second processor.

21. The method of claim 20 , further comprising:

writing, by the first processor, the event log to an internal memory of the microprocessor integrated circuit prior to the first processor resetting the second processor; and

wherein the microcode reading the event log comprises the microcode reading the event log from the internal memory.

22. The method of claim 12 , wherein the debug information comprises information specifying the architectural state of the second processor prior to the first processor resetting the second processor.

23. A computer program product for use with a computing device, the computer program product comprising:

at least one computer readable non-transitory storage medium, having computer readable program code embodied in said medium, for specifying a microprocessor integrated circuit, the computer readable program code comprising:

first program code for specifying first and second processors, wherein the first processor is configured to detect that the second processor has not retired an instruction for a predetermined amount of clock cycles and to responsively reset the second processor; and

second program code for specifying microcode, wherein the second processor is configured to execute the microcode in response to a reset of the second processor, wherein the microcode is configured to read debug information within the microprocessor integrated circuit and to output the debug information external to the microprocessor integrated circuit in response to determining that the reset was performed by the first processor, wherein the microcode is configured to selectively output the debug information on a first or second external bus based on a flag, wherein the first external bus is an architectural bus of the second processor to which a memory external to the microprocessor integrated circuit is coupled, wherein the second external bus is coupled to the first processor, wherein the second external bus is non-architectural to the second processor and is distinct from the architectural bus of the second processor.

24. The computer program product of claim 23 , wherein the flag is user-programmable.

25. The computer program product of claim 23 , wherein the debug information comprises information about the state of signals of an architectural bus of the second processor prior to the reset.

26. The computer program product of claim 23 , wherein the debug information comprises information specifying the architectural state of the second processor prior to the reset.