Method of forming a field effect transistor
View Patent ↗A method of forming a field effect transistor comprises providing a substrate comprising a biaxially strained layer of a semiconductor material. A gate electrode is formed on the biaxially strained layer of semiconductor material. A raised source region and a raised drain region are formed adjacent the gate electrode. Ions of a dopant material are implanted into the raised source region and the raised drain region to form an extended source region and an extended drain region. Moreover, in methods of forming a field effect transistor according to embodiments of the present invention, a gate electrode can be formed in a recess of a layer of semiconductor material. Thus, a field effect transistor wherein a source side channel contact region and a drain side channel contact region located adjacent a channel region are subject to biaxial strain can be obtained.
1. A method of forming a field effect transistor, comprising:
providing a substrate comprising a strained layer of a semiconductor material;
forming a mask on said layer of semiconductor material, said mask having an opening;
forming a recess in a portion of said layer of semiconductor material exposed at a bottom of said opening;
forming a layer of an insulating material on said exposed portion of said layer of semiconductor material;
filling said opening with a gate electrode material;
selectively removing said mask, wherein said gate electrode material in said opening substantially remains on said substrate to form a gate electrode;
implanting ions of a dopant material into portions of said layer of semiconductor material located adjacent said gate electrode, wherein a penetration depth of said ions in said implantation is less than a depth of said recess so that a source side channel contact region and a drain side contact region located adjacent a channel region beneath said gate electrode are not irradiated with ions of said dopant material; and
performing an annealing process to induce a diffusion of said dopant material into said source side channel contact region and said drain side channel contact region.
2. The method of claim 1 , wherein said layer of semiconductor material is biaxially strained.
3. The method of claim 2 , wherein said biaxially strained layer of semiconductor material is provided over a layer of an insulating material.
4. The method of claim 3 , wherein said provision of said substrate comprises:
providing an auxiliary substrate;
forming a strain-creating layer on said auxiliary substrate;
forming said layer of semiconductor material on said strain-creating layer;
forming said layer of insulating material on said substrate;
bonding said auxiliary substrate to said substrate, wherein said layer of semiconductor material contacts said layer of insulating material; and
removing said auxiliary substrate and said strain-creating layer.
5. The method of claim 1 , further comprising reducing a length of said opening.
6. The method of claim 5 , wherein said reduction of said length of said opening comprises:
isotropically depositing a material layer on said substrate; and
anisotropically etching said material layer, a portion of said material layer located on a bottom of said opening being substantially removed in said etching.
7. The method of claim 6 , wherein a material of said material layer is identical to a material of said mask.
8. The method of claim 1 , wherein a length of said gate electrode is less than about 50 nm.