ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
An erase method of a nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first insulating layer, a charge accumulation layer formed in a second area on the first insulating layer, a second insulating layer formed on the charge accumulation layer and a second gate electrode formed on the second insulating layer includes a step of injecting hot holes into the charge accumulation layer from the diffusion region and a step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side.
1 . An erase method of a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first insulating layer, a charge accumulation layer formed in a second area on the first insulating layer, a second insulating layer formed on the charge accumulation layer, and a second gate electrode formed on the second insulating layer, the method comprising steps of:
injecting hot holes into the charge accumulation layer from the diffusion region; and
injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side.
2 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , further comprising a step of:
injecting channel hot electrons into a part of the charge accumulation layer close to a drain region side.
3 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , further comprising a step of:
determining charges in the charge accumulation layer after the steps of injecting hot holes and injecting channel hot electrons into the charge accumulation layer.
4 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , wherein
in the step of injecting hot holes into the charge accumulation layer from the diffusion region, a voltage applied to the diffusion region is set to be higher than a voltage applied to the second gate electrode.
5 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , wherein
in the step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side, a voltage applied to a drain region is set to be lower than a voltage applied to the second gate electrode.
6 . The erase method of a nonvolatile semiconductor memory device according to claim 2 , wherein
in the step of injecting channel hot electrons into a part of the charge accumulation layer close to the drain region side, a voltage applied to the drain region is set to be lower than a voltage applied to the second gate electrode.
7 . The erase method of a nonvolatile semiconductor memory device according to claim 6 , wherein
a difference between the voltage applied to the drain region and the voltage applied to the second gate electrode in the step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side is larger than a difference between the voltage applied to the drain region and the voltage applied to the second gate electrode in the step of injecting channel hot electrons into a part of the charge accumulation layer close to the drain region side.
8 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , wherein
injection of channel hot electrons into the charge accumulation layer is performed with a lower voltage than a voltage in injection of channel hot electrons in normal write operation.
9 . The erase method of a nonvolatile semiconductor memory device according to claim 1 , wherein
injection of channel hot electrons into the charge accumulation layer is performed for a shorter time than a time of injection of channel hot electrons in normal write operation.