SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
A page table management circuit includes a memory control circuit including a memory unit that stores information used to convert a virtual address into a physical address with respect to each entry and designating the entry according to an input address value, and an address conversion circuit converting an input address value such that a total number of the entries to be designated by the memory control circuit is reduced and outputting the converted address value to the memory control circuit.
1 . A semiconductor integrated circuit comprising:
a memory control unit comprising a storage area that stores information used to convert a virtual address into a physical address with respect to each entry, and designating the entry according to an input address value; and
an address conversion unit converting an input address value such that a total number of the entries to be designated by the memory control unit is reduced, and outputting the converted address value to the memory control unit.
2 . The semiconductor integrated circuit according to claim 1 , wherein a bit number of the address value used to designate the entry that is input to the address conversion unit is smaller than a bit number of the address value that is output from the address conversion unit.
3 . The semiconductor integrated circuit according to claim 1 , wherein the address value to be input to the address conversion unit is generated by a CPU core and transmitted from the CPU core to the address conversion unit through an internal bus.
4 . The semiconductor integrated circuit according to claim 1 , wherein the address conversion unit converts an input address value according to an address conversion signal that is transmitted through an internal bus, and outputs the converted address value to the memory control unit.
5 . The semiconductor integrated circuit according to claim 1 , wherein the address conversion unit can operate in a mode in which the input address value is output to the memory control unit without performing any conversion.
6 . The semiconductor integrated circuit according to claim 1 , wherein the address conversion unit is configured so as not to operate in a mode in which the input address value is output to the memory control unit without performing any conversion.
7 . An information processing device comprising:
a memory control circuit comprising a storage area that stores information used to convert a virtual address into a physical address with respect to each entry, and designating the entry according to an input address value;
an address conversion circuit converting an input address value such that a total number of the entries to be designated by the memory control circuit is reduced, and outputting the converted address value to the memory control circuit; and
a CPU core generating the address value to be input to the address conversion circuit, and comprising a retention area that retains one circuit of a plurality of entries stored in the storage area.
8 . The information processing device according to claim 7 , wherein a content of the entry stored in the storage area is reflected on the retention area according to an instruction by the CPU core.
9 . The information processing device according to claim 7 , wherein a bit number of the address value used to designate the entry that is input to the address conversion circuit is smaller than a bit number of the address value that is output from the address conversion circuit.
10 . A control method for a semiconductor integrated circuit, the semiconductor integrated circuit comprising a storage area that stores information used to convert a virtual address into a physical address with respect to each entry, the semiconductor integrated circuit being configured to designate the entry based on an input address value, the method comprising:
converting the input address value generated by a CPU core such that a total number of
the entries to be designated by the address value is reduced; and
designating the entry based on the converted address value.