Process for packaging components, and packaged components
View Patent ↗A wafer level packaging process for packaging components is provided. The process includes permanently connecting a functional side of a base substrate to a covering substrate at wafer level so that a plurality of functional regions on the functional side are in each case packaged to form a wafer level package, the plurality of functional regions being spaced apart from one another on the functional side; producing contact-connection recesses in the base substrate to uncover contact surfaces on the base substrate from a back surface of the base substrate; dividing the base substrate into body regions and connection regions; thinning the body regions or the connection regions until the wafer level package has different thicknesses in the body regions and the connection regions; and dicing wafer level package into chips along predefined cutting lines between the plurality of functional regions.
1. A process for packaging components on a wafer comprising a base substrate having a functional side, on which a functional region of a packaged component is arranged, comprising:
prior to grinding or etching a back surface, bonding a covering substrate to a functional side of the wafer, wherein bonding comprises a single step of gluing, bonding, or adhesively attaching;
uniformly grinding or etching the back surface of the base substrate to a first thickness comprising a reduced component thickness; and
further thinning the back surface of the base substrate in a body region and/or a connection region using a lithographic process to provide different thicknesses between the body region and the connection region,
wherein the further thinning process exposes a contact on the functional side of the wafer; and wherein the contact may be electrically connected to contact surfaces on the connection regions.
2. A process comprising:
in order,
a) processing a wafer to form on a functional side of the wafer one or more functional regions, wherein each functional region has at least one electrical contact, the side of the wafer opposite the functional side comprising a back side of the wafer;
b) bonding a covering substrate to the functional side of the wafer,
c) uniformly thinning the back side of the wafer to a first thickness;
d) selectively thinning the uniformly thinned back side of the wafer in regions corresponding to the one or more functional regions to provide different thicknesses between a body region and a connection region in each corresponding region;
e) further thinning the back side of the wafer to expose the at least one contact on the functional side of the wafer of each functional region;
f) forming an electrical connection between the exposed contact of a functional region and its corresponding connection region; and
g) dicing the wafer to separate each functional region into one or more components.
3. The process according to claim 2 wherein the bonding step b) comprises gluing, bonding or adhesively attaching the covering substrate to the wafer on its functional side.
4. The process according to claim 2 wherein the selective thinning step d) comprises a lithographic process.
5. The process according to claim 2 wherein the further thinning step e) comprises a lithographic process.
6. The process according to claim 2 wherein the uniform thinning step c) comprises grinding or etching.