IP Library Granted Patent US 7,863,609
Granted Patent B2
US 7,863,609 · App. 12/753,535 · Granted Jan 4, 2011

Compound semiconductor substrate, semiconductor device, and processes for producing them

Assignee: Sumitomo Electric Industries, Ltd.
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Quick Facts
Patent No.
US 7,863,609
App. No.
12/753,535
Granted
Jan 4, 2011
Kind
B2
Abstract

A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×10 10 atoms/cm 2 and not more than 12000×10 10 atoms/cm 2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×10 10 atoms/cm 2 and not more than 12000×10 10 atoms/cm 2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.

Claims (9)

1. A compound semiconductor substrate comprised of a Group III nitride and having a surface containing a chloride of not less than 200×10 10 atoms/cm 2 and not more than 12000×10 10 atoms/cm 2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface.

2. The compound semiconductor substrate according to claim 1 , wherein the surface contains the chloride of not less than 300×10 10 atoms/cm 2 and not more than 8000×10 10 atoms/cm 2 in terms of Cl.

3. The compound semiconductor substrate according to claim 1 , wherein the surface contains the oxide of not less than 5.0 at % and not more than 12.0 at % in terms of O.

4. The compound semiconductor substrate according to claim 1 , wherein a surface roughness (RMS) of the surface is not more than 3 nm.

5. The compound semiconductor substrate according to claim 1 , wherein a surface roughness (RMS) of the surface is not more than 1 nm.

6. The compound semiconductor substrate according to claim 1 , wherein the surface has a structure in which low dislocation density regions and high dislocation density regions are alternately arranged.

7. The compound semiconductor substrate according to claim 1 , further comprising an epitaxial layer formed on the surface and comprised of a Group III nitride.

8. The compound semiconductor substrate according to claim 1 , wherein a plane direction of the surface is one of the (0001) plane, (11-20) plane, (10-12) plane, (10-10) plane, (20-21) plane, (10-11) plane, (11-21) plane, (11-22) plane, and (11-24) plane of the wurtzite structure.

9. The compound semiconductor substrate according to claim 1 , wherein the surface has an off-angle of not more than 15° relative to one of the (0001) plane, (11-20) plane, (10-12) plane, (10-10) plane, (20-21) plane, (10-11) plane, (11-21) plane, (11-22) plane, and (11-24) plane of the wurtzite structure.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Dec 7, 2023
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUBISHI CHEMICAL CORPORATION
Reel/Frame 065817/0967 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2010
From: ISHIBASHI, KEIJI; NAKANISHI, FUMITAKE
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 024410/0222 →
Priority Claims (1)
JP P2009-009151 · Jan 19, 2009 · national
Continuity (2)
Continuation PCTJP200905121100 · Jan 26, 2009
Related Publication 20100224963A1 · Sep 9, 2010