Microcontroller peripheral event distribution bus

1. A method of controlling an engine, the method comprising:

a serial bus transmitting a first event-signal;

a parallel bus transmitting a first event-identification (event-ID);

wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur;

wherein the first event-ID corresponds to the first event-signal.

2. The method of claim 1 wherein the serial bus and the parallel bus concurrently transmit the first event-signal and the first event-ID, respectively.

3. The method of claim 2 further comprising:

the serial bus and the parallel bus concurrently transmitting a second event-signal and a second event-ID, respectively;

wherein the second event-signal, when active, indicates that a second event has occurred, is occurring, or should occur;

wherein the second event-ID corresponds to the second event-signal;

wherein the second event-signal and the second event-ID are transmitted after transmission of the first event-signal and the first event-ID.

4. The method of claim 2 wherein a first circuit concurrently transmits the first event-signal and the first event-ID to a plurality of circuits via the serial and parallel buses, respectively.

5. The method of claim 2 further comprising:

a first compare circuit receiving the first event-ID via the parallel bus;

the first compare circuit comparing the first event-ID with data stored in a first memory device;

a first pass circuit receiving the first event-signal via the serial bus;

the first pass circuit passing the first event-signal if the first event-ID compares equally to the data stored in the first memory device.

6. The method of claim 5 further comprising:

a second compare circuit receiving the first event-ID via the parallel bus;

the second compare circuit comparing the first event-ID with data stored in a second memory device;

a second pass circuit receiving the first event-signal via the serial bus;

the first pass circuit passing the first event-signal if the first event-ID compares equally to the data stored in the second memory device.

7. The method of claim 3 wherein a first circuit concurrently transmits the first event-signal and the first event-ID, wherein a second circuit concurrently transmits the second event-signal and the second event-ID in response to the second circuit concurrently receiving the first event-signal and the first event-ID from the first circuit via the serial and parallel buses, respectively.

8. The method of claim 2 further comprising:

a circuit concurrently receiving the first event-signal and the first event-ID;

the circuit generating a control signal for controlling a component of the engine;

wherein the circuit generates the control signal as a function of the first event-signal.

9. The method of claim 2 further comprising:

a first circuit receiving the first event-ID from a processor via a communication bus;

the first circuit storing the first event-ID it receives from the processor into a memory device;

the first circuit concurrently transmitting the first event-signal and the first event-ID after the first circuit stores the first event-ID into the memory device.

10. A system for controlling an engine, the system comprising:

a serial bus;

a parallel bus;

first and second circuits coupled to each other via the serial and parallel buses;

wherein the first circuit is configured to concurrently transmit a first event-signal and a first event-identification (event-ID) to the second circuit via the serial and parallel buses, respectively, wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur, and wherein the first event-ID corresponds to the first event-signal;

wherein the second circuit is configured to concurrently transmit a second event-signal and a second event-ID to the first circuit over the serial and parallel buses, respectively, wherein the second event-signal, when active, indicates that a second event has occurred, is occurring, or should occur, wherein the second event-ID corresponds to the second event-signal;

and wherein the second circuit is configured to concurrently transmit the second event-signal and the second event-ID after the first circuit concurrently transmits the first event-signal and the first event-ID.

11. The system of claim 10 further comprising a third circuit configured to concurrently receive the first event-signal and the first event-ID from the first circuit via the serial and parallel buses, respectively, wherein the third circuit is configured to generate a first control signal for controlling a first component of the engine as a function of the first event-signal.

12. The system of claim 10 further comprising:

a first compare circuit coupled to a first pass circuit;

wherein the first compare circuit is configured to receive the first event-ID via the parallel bus, wherein the first compare circuit is configured to compare the first event-ID with data stored in a first memory device;

wherein the first pass circuit is configured to receive the first event-signal via the serial bus, wherein the first pass circuit is configured to pass the first event-signal if the first event-ID compares equally to the data stored in the first memory device.

13. The system of claim 10 wherein the second circuit is configured to concurrently transmit the second event-signal and the second event-ID in response to the second circuit concurrently receiving the first event-signal and the first event-ID from the first circuit via the serial and parallel buses, respectively.

14. The system of claim 10 further comprising:

a communication bus;

a processor coupled to the first circuit via the communication bus;

wherein the first circuit is configured to receive the first event-ID from the processor via the communication bus;

wherein the first circuit is configured to store the first event-ID it receives from the processor into a memory device of the first circuit;

wherein the first circuit is configured to concurrently transmit the first event-signal and the first event-ID after the first circuit stores the first event-ID into the memory device.

15. The system of claim 10 further comprising:

a bus controller coupled to the first and second circuits;

wherein the first circuit concurrently transmits the first event-signal and the first event-ID only when given permission by the bus controller;

wherein the second circuit concurrently transmits the second event-signal and the second event-ID only when given permission by the bus controller.

16. The system of claim 10 wherein the second circuit comprises a counter, wherein the counter is configured to increment a count in response to the second circuit concurrently receiving the first event-signal and the first event-ID.

17. The system of claim 16 wherein the second circuit further comprises:

a compare circuit configured to compare the count with a predetermined number;

wherein the second circuit is configured to concurrently transmit the second event-signal and the second event-ID in response to the compare circuit comparing the count with the predetermined number.

18. The system of claim 11 further comprising a fourth circuit configured to concurrently receive the second event-signal and the second event-ID from the second circuit via the serial and parallel buses, respectively, wherein the fourth circuit is configured to generate a second control signal for controlling a second component of the engine as a function of the second event-signal.

19. The system of claim 18 wherein the first component comprises a coil coupled to a spark plug, and wherein the second component comprises a fuel injector.

20. A system for controlling an engine, the system comprising:

a serial bus;

a parallel bus;

first and second circuits coupled to each other via the serial and parallel buses;

wherein the first circuit is configured to transmit a first event-signal to the second circuit via the serial bus in response to the first circuit receiving a first event-identification (event-ID) via the parallel bus, wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur, and wherein the first event-ID corresponds to the first event-signal;

wherein the second circuit is configured to transmit a second event-signal to the first circuit via the serial bus in response to the second circuit receiving a second event-ID via the parallel bus, wherein the second event-signal, when active, indicates that a second event has occurred, is occurring, or should occur, wherein the second event-ID corresponds to the second event-signal, and;

wherein the serial and parallel buses transmit the second event-signal and the second event-ID, respectively, after the serial and parallel buses transmit the first event-signal and the first event-ID, respectively.