Dummy pattern in wafer backside routing
View Patent ↗A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.
1. A device comprising:
a semiconductor substrate comprising a front side and a backside;
a through-substrate via (TSV) penetrating the semiconductor substrate; and
a first dummy metal line on the backside of the semiconductor substrate.
2. The device of claim 1 further comprising an active circuit on the front side of the semiconductor substrate, wherein the active circuit comprises a transistor.
3. The device of claim 2 further comprising a dummy TSV penetrating the semiconductor substrate.
4. The device of claim 3 , wherein the first dummy metal line is electrically coupled to the dummy TSV, and wherein the first dummy metal line and the dummy TSV are electrically floating.
5. The device of claim 4 further comprising a second dummy metal line on the front side of the semiconductor substrate, wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
6. The device of claim 4 further comprising:
a plurality of dielectric layers on the backside of the semiconductor substrate;
a plurality of dummy metal lines, with one of the plurality of dummy metal lines in each of the plurality of dielectric layers; and
a plurality of dummy vias electrically coupled to the plurality of dummy metal lines, with the plurality of dummy metal lines, the plurality of dummy vias, and the dummy TSV forming an integrated metal structure.
7. The device of claim 1 further comprising a bond pad on the backside of the semiconductor substrate, and a dummy metal pad at a same level as the bond pad.
8. The device of claim 1 further comprising a dummy via on the backside of the semiconductor substrate and connected to the first dummy metal line.
9. A device comprising:
a semiconductor substrate comprising a front side and a backside;
an active circuit on the front side of the semiconductor substrate;
a through-substrate via (TSV) penetrating the semiconductor substrate;
a dummy TSV penetrating the semiconductor substrate; and
a first dummy metal line on the backside of the semiconductor substrate and electrically coupled to the dummy TSV, wherein the first dummy metal line and the dummy TSV are electrically floating.
10. The device of claim 9 , wherein the first dummy metal line physically contacts the dummy TSV.
11. The device of claim 9 , wherein the semiconductor substrate is a portion of a chip, and wherein the device further comprises:
a bond pad at a back surface of the chip; and
a dummy metal feature at a same level as the bond pad.
12. The device of claim 9 further comprising:
a plurality of dielectric layers on the backside of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, and wherein the plurality of dummy metal features and the dummy TSV form an integrated metal structure.
13. The device of claim 12 further comprising a plurality of dummy vias, each in one of the plurality of dielectric layers and contacting a respective one of the plurality of dummy metal features.
14. The device of claim 9 further comprising a second dummy metal line on the front side of the semiconductor substrate.
15. The device of claim 14 , wherein the second dummy metal line is electrically coupled to the dummy TSV and the first dummy metal line.
16. The device of claim 14 further comprising:
a plurality of dielectric layers on the front side of the semiconductor substrate; and
a plurality of dummy metal features, with each of the plurality of dielectric layers comprising one of the plurality of dummy metal features therein, wherein the plurality of dummy metal features is electrically coupled to the dummy TSV.
17. A device comprising:
a semiconductor substrate comprising a front side and a backside;
an active circuit on the front side of the semiconductor substrate;
a through-substrate via (TSV) penetrating the semiconductor substrate;
a dummy TSV penetrating the semiconductor substrate;
a first plurality of dielectric layers on the backside of the semiconductor substrate;
a first plurality of dummy metal features, with each of the first plurality of dielectric layers comprising one of the first plurality of dummy metal features therein;
a second plurality of dielectric layers on the front side of the semiconductor substrate; and
a second plurality of dummy metal features, with each of the second plurality of dielectric layers comprising one of the second plurality of dummy metal features therein, and wherein the first and the second plurality of dummy metal features and the dummy TSV form an integrated metal structure, and are electrically floating.
18. The device of claim 17 further comprising a bond pad on the backside of the semiconductor substrate, wherein one of the first plurality of dummy metal features is at a same level as the bond pad.
19. The device of claim 17 , wherein one of the first plurality of dummy metal features is a dummy via.
20. The device of claim 2 , wherein the first dummy metal line is electrically floating.