IP Library Granted Patent US 8,404,508
Granted Patent B2
US 8,404,508 · App. 12/756,960 · Granted Mar 26, 2013

Enhancement mode GaN HEMT device and method for fabricating the same

Inventors: Alexander Lidow (Marina Del Ray, CA); Robert Beach (La Crescenta, CA); Alana Nakata (Redondo Beach, CA); Jianjun Cao (Torrance, CA); Guang Yuan Zhao (Torrance, CA)
Assignee: Efficient Power Conversion Corporation
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Quick Facts
Patent No.
US 8,404,508
App. No.
12/756,960
Granted
Mar 26, 2013
Kind
B2
Abstract

An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Claims (64)

1. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an III Nitride EPI layer over the transistor layers;

growing an III Nitride barrier layer over the EPI layer;

growing a GaN layer with acceptor type dopants over the barrier layer;

depositing a gate contact layer on the doped GaN layer;

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer, except a portion of the doped GaN layer beneath the gate contact;

removing the gate photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a metal photo resistant pattern;

etching the Ohmic contact metal;

removing the metal photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.

2. The method of claim 1 , wherein the EPI layer is comprised of InAlGaN.

3. The method of claim 1 , wherein the barrier layer is comprised of InAlGaN with a larger band gap than the buffer layer.

4. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an InAlGaN EPI layer over the transistor layers;

growing an InAlGaN barrier layer over the InAlGaN EPI layer;

growing an InAlGaN layer with acceptor type dopants over the InAlGaN barrier layer;

growing a GaN layer with acceptor type dopants over the doped InAlGaN layer;

depositing a gate contact layer on the doped GaN layer

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer and the doped InAlGaN layer, except for portions of the doped GaN layer and the doped InAlGaN layer beneath gate contact;

removing the gate photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a metal photo resistant pattern;

etching the Ohmic contact metal;

removing the metal photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.

5. A method of forming an enhancement mode GaN transistor, the method comprising:

nucleating and growing transition layers on a substrate;

growing an InAlGaN EPI layer over the transistor layers;

growing an AlGaN barrier layer over the InAlGaN EPI layer;

growing an AlGaN layer with acceptor type dopants over the AlGaN barrier layer;

growing a GaN layer with acceptor type dopants over the doped AlGaN layer;

depositing a gate contact layer on the doped GaN layer

applying a gate photo resistant pattern;

etching away the gate contact layer outside the gate region;

etching away the doped GaN layer, except for portions of the doped GaN layer and the doped AlGaN layer beneath gate contact;

removing the gate photo resistant pattern;

applying another photo resistant pattern;

etching the doped AlGaN layer such that the doped AlGaN extends outside the gate region towards the drain;

removing the photo resistant pattern;

depositing a dielectric layer;

applying a contact photo resistant pattern;

etching the dielectric layer to open the drain and source contact area;

removing the contact photo resistant pattern;

depositing an Ohmic contact metal;

applying a fourth photo resistant pattern;

etching the Ohmic contact metal

removing the fourth photo resistant pattern; and

performing rapid thermal annealing to form Ohmic drain and source contacts.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2010
From: LIDOW, ALEXANDER; BEACH, ROBERT; NAKATA, ALANA; CAO, JIANJUN; ZHAO, GUANG YUAN
To: EFFICIENT POWER CONVERSION CORPORATION
Reel/Frame 024208/0084 →
Continuity (2)
Provisional Application 61167777 · Apr 8, 2009
Related Publication 20100258843A1 · Oct 14, 2010