Method Of Operating A NAND Memory Controller To Minimize Read Latency Time

1 . A method of operating a controller for controlling a NAND memory chip, wherein said NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum amount that is erasable as a group, wherein said method comprising:

writing data into a block to partially fill the block;

tracking the extent to which said block has been written;

stopping the writing after said block is partially written;

detecting if a request to the NAND memory chip needs to be serviced; and

resuming the writing into said block after servicing the request.

2 . The method of claim 1 wherein said request is a read operation.

3 . The method of claim 2 wherein the amount of data written into said block during the writing step is determined by the total amount of time the writing step would take.

4 . The method of claim 3 wherein said block comprises a plurality of pages.

5 . The method of claim 3 wherein said tracking step comprises:

creating an index of the logic address to the new physical address of data written into said block.

6 . The method of claim 5 wherein said resuming step comprises retrieving the index created to determine the extent to which data has been written into the block, and continuing the writing therefrom.

7 . A method of operating a memory device having a controller for interfacing with and controlling a NAND memory, wherein said NAND memory has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum amount that is erasable as a group, wherein said memory device is responsive to parallel ATA protocol commands supplied from a host, wherein said method comprising:

responding to a write command by writing data into a block to partially fill the block;

tracking the extent to which said block has been written;

stopping the writing after said block is partially written;

reporting to the host of the memory device's readiness to receive another command; and

resuming the writing into said block if no read command is received from the host.

8 . The method of claim 7 wherein said request is a read operation.

9 . The method of claim 8 wherein the amount of data written into said block during the writing step is determined by the total amount of time the writing step would take.

10 . The method of claim 9 wherein said block comprises a plurality of pages.

11 . The method of claim 9 wherein said tracking step comprises:

creating an index of the logic address to the new physical address of data written into said block.

12 . The method of claim 11 wherein said resuming step comprises retrieving the index created to determine the extent to which data has been written into the block, and continuing the writing therefrom.

13 . A method of operating a memory device having a controller for interfacing with and controlling a NAND memory, wherein said. NAND memory has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum amount that is erasable as a group, wherein said memory device is responsive to serial ATA protocol commands supplied from a host, wherein said method comprising:

responding to a write command by writing data into a block to partially fill the block;

checking to determine if any request command is received during the step of writing data into the block;

tracking the extent to which said block has been written; and

continuing the writing into said block if no request command is received.

14 . The method of claim 13 wherein said request is a read operation.

15 . The method of claim 14 wherein the amount of data written into said block during the writing step is determined by the total amount of time the writing step would take.

16 . The method of claim 15 wherein said block comprises a plurality of pages.

17 . The method of claim 15 wherein said tracking step comprises:

creating an index of the logic address to the new physical address of data written into said block.

18 . A method of operating a memory device having a controller for interfacing with and controlling a NAND memory, wherein said NAND memory has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum amount that is erasable as a group, wherein said memory device is responsive to serial ATA protocol commands supplied from a host, wherein said method comprising:

responding to a write command by writing data into a block to partially fill the block;

tracking the extent to which said block has been written;

stopping the writing, after said block is partially written;

checking to determine if any request command is received by the memory device after the writing step; and

resuming the writing into said block if no request command is received.

19 . The method of claim 18 wherein said request is a read operation.

20 . The method of claim 19 wherein the amount of data written into said block during the writing step is determined by the total amount of time the writing step would take.

21 . The method of claim 20 wherein said block comprises a plurality of pages.

22 . The method of claim 20 wherein said tracking step comprises:

creating an index of the logic address to the new physical address of data written into said block.

23 . The method of claim 22 wherein said resuming step comprises retrieving the index created to determine the extent to which data has been written into the block, and continuing the writing therefrom.