Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period
View Patent ↗When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.
1. A semiconductor memory device comprising:
a memory element comprising a first electrode, a second electrode, and a semiconductor layer between the first electrode and the second electrode;
a boosting circuit configured to generate a writing voltage, an output terminal of the boosting circuit being electrically connected to the memory element; and
a monitor circuit electrically connected to the output terminal of the boosting circuit,
wherein the monitor circuit comprises a comparator, a first resistor, a second resistor, a third resistor, a fourth resistor and a NAND gate,
wherein a first terminal of the first resistor is electrically connected to the output terminal of the boosting circuit,
wherein a second terminal of the first resistor is electrically connected to a first terminal of the second resistor and a first input terminal of the comparator,
wherein a first voltage is applied to a first terminal of the third resistor.
wherein a second terminal of the third resistor is electrically connected to a first terminal of the fourth resistor and a second input terminal of the comparator,
wherein a second voltage is applied to a second terminal of the second resistor and a second terminal of the fourth resistor,
wherein an output of the comparator is input to the NAND gate,
wherein the monitor circuit is configured to detect a voltage change in the output terminal of the boosting circuit in a writing operation on the memory element and output a signal to stop the writing operation on the memory element from the NAND gate, and
wherein the boosting circuit is configured to stop a boosting operation by stopping a supply of a clock signal to the boosting circuit in accordance with the signal.
2. The semiconductor memory device according to claim 1 ,
wherein the memory element is configured to store data in such a way that the writing voltage is applied between the first electrode and the second electrode to change a value of resistance between the first electrode and the second electrode.
3. An electronic device comprising the semiconductor memory device according to claim 1 .
4. A semiconductor memory device comprising:
a memory element comprising a first electrode, a second electrode, and a semiconductor layer between the first electrode and the second electrode;
a boosting circuit configured to generate a writing voltage, an output terminal of the boosting circuit being electrically connected to the memory element;
a control circuit configured to input a signal to the boosting circuit; and
a monitor circuit electrically connected to the output terminal of the boosting circuit, the monitor circuit being configured to control the control circuit,
wherein the monitor circuit comprises a comparator, a first resistor, a second resistor, a third resistor, a fourth resistor and a NAND gate,
wherein a first terminal of the first resistor is electrically connected to the output terminal of the boosting circuit,
wherein a second terminal of the first resistor is electrically connected to a first terminal of the second resistor and a first input terminal of the comparator,
wherein a first voltage is applied to a first terminal of the third resistor,
wherein a second terminal of the third resistor is electrically connected to a first terminal of the fourth resistor and a second input terminal of the comparator,
wherein a second voltage is applied to a second terminal of the second resistor and a second terminal of the fourth resistor,
wherein an output of the comparator is input to the NAND gate, and
wherein the boosting circuit is configured to stop a boosting operation by stopping a supply of a clock signal to the boosting circuit in accordance with the signal.
5. The semiconductor memory device according to claim 4 ,
wherein the signal is a signal for stopping the boosting operation of the boosting circuit.
6. The semiconductor memory device according to claim 4 ,
wherein the memory element stores data in such a way that the writing voltage is applied between the first electrode and the second electrode to change a value of resistance between the first electrode and the second electrode.
7. An electronic device comprising the semiconductor memory device according to claim 4 .
8. A semiconductor memory device comprising:
a memory element;
a boosting circuit; and
a monitor circuit comprising a comparator, a first resistor, a second resistor, a third resistor. a fourth resistor and a NAND gate,
wherein a first terminal of the first resistor is electrically connected to an output terminal of the boosting circuit,
wherein a second terminal of the first resistor is electrically connected to a first terminal of the second resistor and a first input terminal of the comparator,
wherein a first voltage is applied to a first terminal of the third resistor,
wherein a second terminal of the third resistor is electrically connected to a first terminal of the fourth resistor and a second input terminal of the comparator,
wherein a second voltage is applied to a second terminal of the second resistor and a second terminal of the fourth resistor,
wherein an output of the comparator is input to the NAND gate,
wherein the output terminal of the boosting circuit is electrically connected to the memory element,
wherein the monitor circuit is electrically connected to the output terminal of the boosting circuit,
wherein an input terminal of the comparator is electrically connected to the output terminal of the boosting circuit, and
wherein the boosting circuit is configured to stop a boosting operation by stopping a supply of a clock signal to the boosting circuit in accordance with an output from the NAND gate.
9. The semiconductor memory device according to claim 8 ,
wherein the memory element comprises a first electrode, a second electrode, and a semiconductor layer between the first electrode and the second electrode, and
wherein the memory element stores data in such a way that a writing voltage is applied between the first electrode and the second electrode to change a value of resistance between the first electrode and the second electrode.
10. An electronic device comprising the semiconductor memory device according to claim 8 .