Liquid crystal display device and fabricating method thereof
A liquid crystal display device may comprise a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has a side surface of a substantially tapered shape; a gate insulating layer covering the semiconductor layer; a gate electrode on the gate insulating layer and substantially corresponding to the channel portion; source and drain electrodes contacting the semiconductor layer; and a pixel electrode contacting the drain electrode.
1. A liquid crystal display device, comprising:
a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has at least two steps to have a stair shape;
a gate insulating layer covering the semiconductor layer;
a gate electrode on the gate insulating layer and substantially overlapping the channel portion;
source and drain electrodes contacting the semiconductor layer; and
a pixel electrode contacting the drain electrode.
2. The device according to claim 1 , wherein the gate insulating layer has a step portion by a height of the edge portion of the semiconductor layer, and the step portion of the gate insulating layer is has substantially the same thickness as other portions of the gate insulating layer.
3. The device according to claim 1 , wherein the semiconductor layer includes poly-crystalline silicon.
4. The device according to claim 1 , wherein the semiconductor layer further includes lightly doped drain portions substantially between the channel portion and the ohmic contact portions.
5. A method of fabricating a liquid crystal display device, comprising:
forming a semiconductor layer on a substrate and including a channel portion and ohmic contact portions at both sides of the channel portion, wherein an edge portion of the semiconductor layer has at least two steps to have a stair shape;
forming a gate insulating layer covering the semiconductor layer;
forming a gate electrode on the gate insulating layer and substantially overlapping the channel portion;
forming source and drain electrodes contacting the semiconductor layer; and
forming a pixel electrode contacting the drain electrode.
6. The method according to claim 5 , wherein forming the at least two steps includes:
forming a poly-crystalline silicon layer;
forming a photoresist pattern on the poly-crystalline silicon layer;
first-dry-etching the poly-crystalline silicon layer using the photoresist pattern;
ashing the photoresist pattern; and
second-dry-etching the first-dry-etched poly-crystalline silicon layer using the ashed photoresist pattern,
wherein the first-dry-etching, ashing and second-dry-etching processes are repeated at least one time.
7. The method according to claim 6 , wherein forming the ohmic contact portions includes doping the semiconductor layer with n+ or p+-ions using the gate electrode as a doping mask after forming the at least two steps.
8. The method according to claim 5 , wherein the gate insulating layer has a step portion by a height of the edge portion of the semiconductor layer, and the step portion of the gate insulating layer has substantially the same thickness as other portions of the gate insulating layer.
9. The method according to claim 5 , wherein forming the semiconductor layer includes forming lightly doped drain portions substantially between the channel portion and the ohmic contact portions.