Data processing system and method
View Patent ↗A data processing device is provided. The data processing device includes a first port configured to receive data from a first bus, and a direct memory access (DMA) engine coupled to the first port. The DMA engine is configured to receive the data from the first bus, receive a contiguous scatter-gather list from a processing device via a second port, configure the data according to the contiguous scatter-gather list, and provide the configured data to the processing device through the second port. The second port is configured to write the configured data to the processing device over a second bus.
1. A data processing device comprising:
a first port configured to receive compressed digital video data from a first bus;
a direct memory access (DMA) engine coupled to the first port configured as a peripheral component interconnect (PCI) master, and further configured to:
receive the compressed digital video data from the first bus;
receive a contiguous scatter-gather list from a processing device via a second port;
configure the compressed digital video data according to the contiguous scatter-gather list; and
provide the configured data to the processing device through the second port using a PCI write and acting as a PCI master; and
the second port configured to write the configured data to the processing device over a second bus configured as a PCI bus.
2. The data processing device of claim 1 , wherein the first bus is a local bus.
3. The data processing device of claim 1 , wherein the second bus is a PCI Express (PCI-E) bus.
4. The data processing device of claim 1 , wherein the data is video data from a video capture device.
5. The data processing device of claim 1 , wherein the data is compressed digital video data from a video capture device.
6. The data processing device of claim 1 , wherein the contiguous scatter-gather list is received from the processing device in a single DMA operation.
7. The data processing device of claim 1 , wherein the DMA engine is an application specific integrated circuit (ASIC).
8. The data processing device of claim 7 , wherein the DMA engine is a field programmable gate array (FPGA).
9. A method for the operation of a data processing device configured as a peripheral component interconnect (PCI) master, the method comprising:
receiving compressed digital video data through a first port from a first bus;
receiving a contiguous scatter-gather list through a second port from a second bus configured as a PCI bus;
configuring the compressed digital video data according to the contiguous scatter-gather list, resulting in configured data; and
writing the configured data to a processing device through the second port and the second bus using a PCI write and acting as a PCI master.
10. The method of claim 9 , wherein the first bus is a local bus.
11. The method of claim 9 , wherein the second bus is a PCI Express (PCI-E) bus.
12. The method of claim 9 , wherein the data is video data from a video capture device.
13. The method of claim 9 , wherein the data is compressed digital video data from a video capture device.
14. The method of claim 9 , wherein the contiguous scatter-gather list is received from the processing device in a single DMA operation.
15. The method of claim 9 , wherein the data processing device is an application specific integrated circuit (ASIC).
16. The method of claim 15 , wherein the data processing device is a field programmable gate array (FPGA).
17. A video system comprising:
a video capture device configured to capture video data of a scene;
a video decoder coupled to the video capture device, configured to translate captured video data to digital video data;
a video compressor coupled to the video decoder, configured to compress the digital video data resulting in compressed digital video data;
a data processor coupled to the video compressor, comprising:
a first port configured to receive compressed digital video data from the video compressor;
a direct memory access (DMA) engine coupled to the first port, configured to receive compressed digital video data from the first port; and
a second port configured to write configured video data to a peripheral component interconnect (PCI) bus;
a video processor coupled to the data processor, configured to receive configured video data from the data processor through the PCI bus; and
a memory device coupled to the video processor, configured to store configured video data;
wherein the DMA engine is configured to:
receive a contiguous scatter-gather list at the second port from the video processor through the PCI bus;
configure the compressed video data according to the contiguous scatter-gather list resulting in configured video data; and
write the configured video data to the video processor through the second port and the PCI bus using a PCI write and acting as a PCI master;
wherein the video processor is configured to store the configured video data in the memory device.
18. The video system of claim 17 , wherein the bus is a PCI Express (PCI-E) bus.