Ultra-low power multi-threshold asynchronous circuit design
View Patent ↗A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.
1. An early completion input incomplete asynchronous circuit (ECII), the ECII comprising:
a delay insensitive register having a data input, a data output, a request input, and an acknowledge output;
a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and an output coupled to a data input of a delay insensitive register of a subsequent ECII; and
an early completion circuit having a first input coupled to the acknowledge output, a second input coupled to the request input, and an output coupled to the sleep input and to a request input of a delay insensitive register of a previous ECII.
2. The circuit of claim 1 , wherein the acknowledge output includes a plurality of acknowledge signals.
3. The circuit of claim 1 , wherein the early completion circuit outputs a request for data when the first input is a null and the second input is a request for null.
4. The circuit of claim 1 , wherein the early completion circuit outputs a request for null when the first input is a data and the second input is a request for data.
5. The circuit of claim 1 , wherein the early completion circuit maintains its output until the first and second inputs are null/request for null or data/request for data.
6. The circuit of claim 1 , wherein the multi-threshold null convention logic circuit is one of a static multi-threshold null convention logic with hold1 circuit and a semi-static multi-threshold null convention logic with hold1 circuit.
7. A fixed early completion input incomplete asynchronous circuit (FECII), the FECII comprising:
a delay insensitive register having a data input, a data output, a request input, and an acknowledge output;
a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and an output coupled to a data input of a delay insensitive register of a subsequent FECII;
an early completion circuit having a first input coupled to the acknowledge output, a second input coupled to an output of an early completion circuit of a subsequent FECII, and an output coupled to the sleep input and to an input of an early completion circuit of a previous FECII; and
an inverter coupled to the output of the early completion circuit and having an output coupled to the request input.
8. The circuit of claim 7 , wherein the first acknowledge output, the second acknowledge output, and the third acknowledge output each include a plurality of acknowledge signals.
9. The circuit of claim 7 , wherein the early completion circuit outputs a request for data when the first input is a null and the second input is a request for null.
10. The circuit of claim 7 , wherein the early completion circuit outputs a request for null when the first input is a data and the second input is a request for data.
11. The circuit of claim 7 , wherein the early completion circuit maintains its output until the first and second inputs are null/request for null or data/request for data.
12. The circuit of claim 7 , wherein each of the multi-threshold null convention logic circuit is one of a static multi-threshold null convention logic with hold1 circuit, a semi-static multi-threshold null convention logic with hold1 circuit, a static multi-threshold null convention logic circuit, and a semi-static multi-threshold null convention logic circuit.
13. An early completion input incomplete asynchronous circuit (ECII), the circuit comprising:
a delay insensitive register having a data input and a data output;
a multi-threshold null convention logic circuit having a data input coupled to the delay insensitive register data output, a sleep input, and a data output; and
a slept early completion circuit having a first input coupled to an output of an early completion circuit of a subsequent ECII, a second input coupled to the output of an early completion circuit of a previous ECII, a third input coupled to the delay insensitive register data input, and an output coupled to the sleep input.
14. The circuit of claim 13 , wherein the delay insensitive register includes a request input coupled to the slept early completion circuit first input.
15. The circuit of claim 13 , wherein the delay insensitive register is a slept delay insensitive register and includes a sleep input coupled to the slept early completion circuit output.
16. The circuit of claim 13 , wherein the slept early completion circuit outputs a request for data when the first input is a request for data and the second input is a request for null.
17. The circuit of claim 13 , wherein the early completion circuit outputs a request for null when the first input is a request for null, the second input is a request for data, and the third input is a data.
18. The circuit of claim 13 , wherein the early completion circuit maintains its output as a request for null until the first input is a request for data and the second input is a request for null.
19. The circuit of claim 13 , wherein the early completion circuit maintains its output as a request for data until the first input is a request for null, the second input is a request for data, and the third input is a data.
20. The circuit of claim 13 , wherein each of the multi-threshold null convention logic circuit is one of a static multi-threshold null convention logic with hold1 circuit, a semi-static multi-threshold null convention logic with hold1 circuit, a static multi-threshold null convention logic circuit, and semi-static multi-threshold null convention logic circuit.