Light emitting device having vertically stacked light emitting diodes
View Patent ↗Disclosed is a light emitting device having vertically stacked light emitting diodes. It comprises a lower semiconductor layer of a first conductive type positioned on a substrate, a semiconductor layer of a second conductive type on the lower semiconductor layer of a first conductive type, and an upper semiconductor layer of a first conductive type on the semiconductor layer of a second conductive type. Furthermore, a lower active layer is interposed between the lower semiconductor layer of a first conductive type and the semiconductor layer of a second conductive type, and an upper active layer is interposed between the semiconductor layer of a second conductive type and the upper semiconductor layer of a first conductive type. Accordingly, there is provided a light emitting device having a structure in which a lower light emitting diode comprising the lower active layer and an upper light emitting diode comprising the upper active layer are vertically stacked. Therefore, light output per unit area of the light emitting device is enhanced as compared with a conventional light emitting device, and thus, a chip area of the light emitting device needed to obtain the same light output as the conventional light emitting device can be reduced.
1. A light emitting device having vertically stacked light emitting diodes, comprising:
a substrate;
a first light emitting diode, comprising;
a lower semiconductor layer of a first conductive type positioned on the substrate;
a lower semiconductor layer of a second conductive type positioned on the lower semiconductor layer of the first conductive type;
a lower active layer interposed between the lower semiconductor layer of the first conductive type and the lower semiconductor layer of the second conductive type;
a second light emitting diode, comprising:
an upper semiconductor layer of the second conductive type positioned on the lower semiconductor layer of the second conductive type and comprising a GaN-based P-type semiconductor layer;
an upper semiconductor layer of the first conductive type positioned on the upper semiconductor layer of the second conductive type; and
an upper active layer interposed between the upper semiconductor layer of the second conductive type and the upper semiconductor layer of the first conductive type;
a separating layer
interposed between the lower semiconductor layer of the second conductive type and the upper semiconductor layer of the second conductive type,
the separating layer electrically separating the first and second light emitting diodes; and
a codoped layer interposed between the lower semiconductor layer of the first conductive type and the lower active layer or between the upper semiconductor layer of the second conductive type and the upper active layer.
2. The light emitting device as claimed in claim 1 , wherein the separating layer is a semi-insulating layer.
3. The light emitting device of claim 1 , wherein the first conductive type comprises N-type conductivity, and the second conductive type comprises P-type conductivity.
4. The light emitting device of claim 3 , further comprising a lower N-type electrode positioned on the lower semiconductor layer of the first conductive type, and an upper N-type electrode positioned on the upper semiconductor layer of the first conductive type,
wherein the lower N-type electrode and the upper N-type electrode comprise indium tin oxide (ITO).
5. The light emitting device of claim 1 , wherein the upper semiconductor layer of the second conductive type is doped with Mg.
6. The light emitting device of claim 5 , wherein the codoped layer comprises a GaN-based semiconductor layer doped with Mg and Si.
7. The light emitting device of claim 6 , wherein the codoped layer is interposed between the upper semiconductor layer of the second conductive type and the upper active layer, and the codoped layer is configured to increase the internal quantum efficiency of the light emitting device.
8. A light emitting device having a plurality of light emitting cells formed on a substrate, wherein each of the light emitting cells comprises:
a first light emitting diode, comprising;
a lower semiconductor layer of a first conductive type positioned on the substrate;
a lower semiconductor layer of a second conductive type positioned on one region of the lower semiconductor layer of the first conductive type; and
a lower active layer interposed between the lower semiconductor layer of the first conductive type and the lower semiconductor layer of the second conductive type;
a second light emitting diode, comprising:
an upper semiconductor layer of the second conductive type positioned on one region of the lower semiconductor layer of the second conductive type and comprising a GaN-based P-type semiconductor layer;
an upper semiconductor layer of the first conductive type positioned on one region of the upper semiconductor layer of the second conductive type;
an upper active layer interposed between the upper semiconductor layer of the second conductive type and the upper semiconductor layer of the first conductive type; and
a separating layer interposed between the lower semiconductor layer of the second conductive type and the upper semiconductor layer of the second conductive type, the separating layer electrically separating the first and second light emitting diodes,
wherein each of the light emitting cells further comprises a codoped layer interposed between the lower semiconductor layer of the first conductive type and the lower active layer or between the upper semiconductor layer of the second conductive type and the upper active layer.
9. The light emitting device as claimed in claim 8 , wherein the separating layer is a semi-insulating layer.
10. The light emitting device of claim 8 , wherein the first conductive type comprises N-type conductivity, and the second conductive type comprises P-type conductivity.
11. The light emitting device of claim 10 , wherein each of the light emitting cells further comprises a lower N-type electrode positioned on the lower semiconductor layer of the first conductive type, and an upper N-type electrode positioned on the upper semiconductor layer of the first conductive type,
wherein the lower N-type electrode and the upper N-type electrode comprise indium tin oxide (ITO).