Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization
View Patent ↗Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
1. A method of fabricating sophisticated gate electrode structures, comprising:
forming a gate dielectric material above a semiconductor region of a semiconductor device, said gate dielectric material comprising a high-k dielectric material;
forming a metal-containing material above said gate dielectric material, said metal-containing material comprising a threshold adjusting species;
performing a heat treatment to diffuse a portion of said threshold adjusting species into said gate dielectric material;
removing said metal-containing material from above said gate dielectric material;
performing a treatment to stabilize said gate dielectric material;
forming a metal-containing electrode material on said gate dielectric material; and
forming a gate electrode structure of a transistor on a basis of said metal-containing electrode material and said gate dielectric material.
2. The method of claim 1 , wherein performing a treatment to stabilize said gate dielectric material comprises incorporating at least one of nitrogen and oxygen into said high-k dielectric material.
3. The method of claim 1 , wherein performing a treatment to stabilize said gate dielectric material comprises incorporating at least one of nitrogen and oxygen into a base layer of said gate dielectric material.
4. The method of claim 1 , further comprising forming a protection layer above said metal-containing material and performing said heat treatment in the presence of said protection layer.
5. The method of claim 4 , wherein said protection layer comprises silicon.
6. The method of claim 1 , wherein said metal-containing material comprises one of lanthanum and aluminum.
7. The method of claim 6 , wherein said metal-containing material comprises lanthanum and said method further comprises forming an N-channel transistor on the basis of said gate electrode structure.
8. The method of claim 6 , wherein said metal-containing material comprises aluminum and said method further comprises forming a P-channel transistor on the basis of said gate electrode structure.
9. The method of claim 8 , further comprising forming a semiconductor alloy on said semiconductor region prior to forming said gate dielectric material.
10. The method of claim 1 , further comprising forming a liner at least on sidewalls of said gate electrode structure.
11. A method of fabricating sophisticated gate electrode structures, comprising:
forming a gate dielectric material above a first active region and a second active region;
forming a first metal-containing material selectively above said first active region;
forming a second metal-containing material above said second active region;
performing a heat treatment to initiate diffusion of a first species from said first metal-containing material in said gate dielectric material above said first active region and to initiate diffusion of a second species from said second metal-containing material into said gate dielectric material above said second active region;
removing said first and second metal-containing materials; and
performing a treatment to stabilize said gate dielectric material.
12. The method of claim 11 , further comprising forming a metal-containing electrode material on said gate dielectric material and forming a first gate electrode structure above said first active region and a second gate electrode structure above said second active region.
13. The method of claim 12 , further comprising forming a protection layer above said first and second metal-containing materials and performing said heat treatment in the presence of said protection layer.
14. The method of claim 11 , wherein forming said first metal-containing material comprises forming a first cap layer, forming a first diffusion layer containing said first species on said first cap layer and forming a second cap layer on said first diffusion layer.
15. The method of claim 14 , wherein forming said second metal-containing material comprises removing at least said second cap layer and said first diffusion layer from above said second active region and forming a second diffusion layer containing said second species above said first and second active regions.
16. The method of claim 11 , wherein forming said gate dielectric material comprises forming a high-k dielectric material above said first and second active regions.
17. The method of claim 16 , further comprising forming a threshold adjusting semiconductor alloy on said active region prior to forming said gate dielectric material.
18. The method of claim 17 , wherein said first gate electrode structure represents a gate electrode structure of a P-channel transistor.