Generation of multiple diameter nanowire field effect transistors
A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.
1. A method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising:
forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses; and
reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.
2. The method according to claim 1 , wherein the forming comprises:
masking the semiconductor pads and the nanowire channels at one of the first or second regions; and
thinning the semiconductor at the unmasked one of the first or second regions.
3. The method according to claim 1 , wherein the forming comprises:
masking the semiconductor pads and the nanowire channels at one of the first or second regions; and
adding semiconductor material to the unmasked one of the first or second regions.
4. A method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising:
forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions;
thinning the semiconductor at one of the first and second regions more than at the other; and
prior to and/or following the thinning, reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the thinning.
5. The method according to claim 4 , further comprising forming a respective gate surrounding each of the nanowires.
6. The method according to claim 5 , wherein the gates each comprise a dielectric, a thin gate conductor and doped conductive material.
7. The method according to claim 5 , wherein the nanowires each have respective drive currents and/or threshold voltages that differ in accordance with the differences between the initial semiconductor thicknesses.
8. The method according to claim 4 , wherein the thinning comprises masking one of the first or the second regions and thinning the unmasked region.
9. The method according to claim 8 , wherein the thinning of the unmasked region comprises one of oxidation and etching.
10. The method according to claim 8 , wherein the thinning of the unmasked region is repeated at least once.
11. The method according to claim 8 , wherein the masking comprises encapsulating one of the first or the second region with a high and/or low threshold voltage mask.
12. The method according to claim 4 , further comprising at least one of unmasked annealing and reducing sizes of each of the nanowires at the first and second regions.
13. The method according to claim 4 , wherein the differences between the respective thicknesses are reflective of the thinning of the semiconductor at the one of the first and second regions more than at the other.
14. The method according to claim 4 , wherein the differences between the respective thicknesses are equal to or greater than differences resulting from the thinning of the semiconductor at the one of the first and second regions more than at the other.
15. A method of modifying a wafer having a semiconductor disposed on an insulator, the method comprising:
forming pairs of semiconductor pads connected via respective nanowire channels at first and second regions of the wafer;
masking one of the first and second regions of the wafer;
thinning the semiconductor of the unmasked region such that the first and second regions have different semiconductor thicknesses; and
prior to and/or following the thinning, reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the thinning.
16. The method according to claim 15 , further comprising repeating the thinning at least once.
17. A method of forming a device on a wafer having a silicon-on-insulator (SOI) structure disposed on a buried oxide (BOX) layer, the method comprising:
forming pairs of SOI pads connected via respective nanowire channels at first and second regions of the wafer;
masking one of the first and second regions of the wafer;
thinning the SOI pads and the nanowire channels of the unmasked region such that the SOI pads and the nanowire channels of each of the first and second regions have different material thicknesses; and
prior to and/or following the thinning, reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the thinning.
18. The method according to claim 17 , wherein each of the nanowires has a drive current and/or a threshold voltage reflective of the nanowire thickness.
19. The method according to claim 17 , further comprising additionally thinning each of the nanowires at a similar rate.
20. The method according to claim 17 , further comprising additionally thinning each of the nanowires at a unique rate.
21. The method according to claim 17 , further comprising surrounding each of the nanowires with a gate structure.
22. The method according to claim 21 , wherein the surrounding of each of the nanowires with the gate structure comprises surrounding each of the nanowires with dielectric material, gate conductive material and doped conductive material.