Method of fabricating metal oxide semiconductor transistor

1. A method of fabricating a MOS transistor, comprising:

providing a semiconductor substrate;

forming at least a gate on the semiconductor substrate;

forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate;

forming at least a recess within the semiconductor substrate adjacent to the gate;

forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and

forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

2. The method of claim 1 , further comprising a step of removing the protective layer after forming the epitaxial layer in the recess.

3. The method of claim 1 , wherein the protective layer comprises silicon nitride.

4. The method of claim 3 , wherein the protective layer has a thickness of about 150 to 250 angstroms.

5. The method of claim 1 , wherein the spacer further comprises an oxide liner and a nitride spacer.

6. The method of claim 1 , wherein the spacer further comprises an offset spacer, positioned between the gate and the spacer.

7. The method of claim 1 , further comprising a step of forming a source/drain region within the semiconductor substrate adjacent to the gate after forming the spacer.

8. The method of claim 1 , further comprising a step of forming a lightly doped region within the semiconductor substrate adjacent to the gate.

9. The method of claim 1 , further comprising:

forming a lightly doped region in the semiconductor substrate adjacent to the gate after forming the epitaxial layer;

forming the spacer on the sidewall of the gate and on the portion of the epitaxial layer after forming the lightly doped region; and

forming a source/drain region in the semiconductor substrate adjacent to the spacer.

10. A method of fabricating a CMOS transistor, comprising:

providing a semiconductor substrate having at least a first conductive transistor area for fabricating first conductive transistors and at least a second conductive transistor area for fabricating second conductive transistors, and an isolation structure between the first conductive transistor area and the second conductive transistor area;

forming a gate on the first conductive transistor area and on the second conductive transistor area respectively;

forming a first protective layer on the semiconductor substrate, and the first protective layer covering the surface of each gate;

forming at least a first recess within the semiconductor substrate adjacent to the gate in the first conductive transistor area;

forming a first epitaxial layer in the first recess, wherein the top surface of the first epitaxial layer is above the surface of the semiconductor substrate; and

forming a spacer on the sidewall of each gate and at least on a portion of the first epitaxial layer, wherein a contact surface of the first epitaxial layer and the spacer is above the surface of the semiconductor substrate.

11. The method of claim 10 , further comprising a step of forming a first ion lightly doped region within the semiconductor substrate adjacent to the gate in the first conductive transistor area.

12. The method of claim 10 , wherein the first protective layer comprises silicon nitride.

13. The method of claim 10 , wherein the first protective layer has a thickness of about 150 to 250 angstroms.

14. The method of claim 10 , wherein each spacer further comprises an oxide liner and a nitride spacer.

15. The method of claim 10 , wherein each spacer further comprises an offset spacer, positioned between each gate and each spacer.

16. The method of claim 10 , further comprising a step of removing the first protective layer after forming the first epitaxial layer in the first recess.

17. The method of claim 16 , after removing the first protective layer, the method further comprising:

forming a second protective layer on the semiconductor substrate, and the second protective layer covering the surface of each gate;

forming at least a second recess within the semiconductor substrate adjacent to the gate in the second conductive transistor area;

forming a second epitaxial layer in the second recess;

removing the second protective layer; and

forming a second ion lightly doped region within the semiconductor substrate adjacent to the gate in the second conductive transistor area before forming the spacer.

18. The method of claim 17 , wherein the second protective layer comprises silicon nitride.

19. The method of claim 18 , wherein the second protective layer has a thickness of about 150 to 250 angstroms.

20. The method of claim 10 , after forming the first epitaxial layer, the method further comprising:

forming at least a second recess within the semiconductor substrate adjacent to the gate in the second conductive transistor area;

forming a second epitaxial layer in the second recess;

removing the first protective layer; and

forming a second ion lightly doped region within the semiconductor substrate adjacent to the gate in the second conductive transistor area before forming the spacer.

21. The method of claim 10 , wherein the first conductive transistors comprise PMOS transistors and the second conductive transistors comprise NMOS transistors.

22. The method of claim 10 , wherein the first conductive transistors comprise NMOS transistors and the second conductive transistors comprise PMOS transistors.