IP Library Granted Patent US 8,284,566
Granted Patent B2
US 8,284,566 · App. 12/782,041 · Granted Oct 9, 2012

Electronic substrate

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Quick Facts
Patent No.
US 8,284,566
App. No.
12/782,041
Granted
Oct 9, 2012
Kind
B2
Abstract

The electronic substrate includes: a substrate having a first face on which an active element is formed, and a second face on an opposite side to the first face and on which a passive element is formed; and an insulating layer including insulating resin and provided on the substrate, wherein the passive element is formed on the insulating layer, and further comprising: an interconnection pattern arranged on or above the second face of the substrate, wherein the passive element is configured from one part of the interconnection pattern, and a resin layer provided on the second face of the substrate, wherein at least one part of the passive element is formed on the resin layer.

Claims (35)

1. An electronic substrate comprising:

a substrate having

a first face on which an active element is formed, and

a second face on an opposite side to the first face and on which a passive element is formed; and

an insulating layer including insulating resin and provided on the substrate, wherein

the passive element is formed on the insulating layer, and

further comprising: an interconnection pattern arranged on or above the second face of the substrate, wherein the passive element is configured from one part of the interconnection pattern, and

a resin layer provided on the second face of the substrate, wherein at least one part of the passive element is formed on the resin layer.

2. The electronic substrate according to claim 1 , wherein the resin layer functions as stress relieving.

3. The electronic substrate according to claim 1 , wherein the active element is semiconductor device.

4. The electronic substrate according to claim 1 , further comprising:

a penetrative conductive portion penetrating through the substrate; and

an electrode formed on the first face, wherein

the passive element is electrically connected to the electrode via the penetrative conductive portion.

5. The electronic substrate according to claim 1 , wherein the interconnection pattern is formed by laminated layers, and the passive element is configured from one part of the interconnection pattern.

6. The electronic substrate according to claim 1 , further comprising:

an external connection terminal, wherein at least one part of the interconnection pattern is the external connection terminal.

7. The electronic substrate according to claim 6 , further comprising:

an electronic component packaged on the surface of the external connection terminal.

8. The electronic substrate according to claim 7 , wherein the passive element is contained in the electronic component.

9. The electronic substrate according to claim 6 , wherein a plurality of the substrates is connected together via the external connection terminal and is laminated.

10. The electronic substrate according to claim 1 , further comprising:

a ground electrode film formed on the second face of the substrate.

11. The electronic substrate according to claim 10 , wherein the ground electrode film is formed in correspondence with the arrangement of the active region formed on the first face of the substrate.

12. The electronic substrate according to claim 1 , further comprising:

a protective film formed on the second face of the substrate and protecting at least the passive element.

13. The electronic substrate according to claim 1 , further comprising:

a second passive element provided on the first face of the substrate.

14. The electronic substrate according to claim 13 , wherein the second passive element is configured from one part of an interconnection pattern arranged on or above the first face of the substrate.

15. The electronic substrate according to claim 13 , wherein the second passive element is provided in a device packaged on or above the first face of the substrate.

16. An electronic device comprising:

the electronic substrate according to claim 1 , packaged in the electronic device.

17. The electronic substrate according to claim 10 , wherein the ground electrode film is provided opposite to the active region.

18. The electronic substrate according to claim 10 , wherein the ground electrode film is provided between the active region and the passive element.

19. The electronic substrate according to claim 10 , wherein the ground electrode film is provided so that the ground electrode film electromagnetically shields the active region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: SEIKO EPSON CORPORATION
To: ADVANCED INTERCONNECT SYSTEMS LIMITED
Reel/Frame 044938/0869 →