IP Library Granted Patent US 8,416,578
Granted Patent B2
US 8,416,578 · App. 12/782,076 · Granted Apr 9, 2013

Manufacturing method for an electronic substrate

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,416,578
App. No.
12/782,076
Granted
Apr 9, 2013
Kind
B2
Abstract

The manufacturing method for electronic substrate includes: forming an active region on a first face of a substrate; forming a first part of an interconnection pattern as a passive element on a second face of the substrate; forming an insulating layer as a stress-relieving layer on the second face of the substrate; and forming a second part of the interconnection pattern as the passive element on the insulating layer.

Claims (11)

1. A manufacturing method for an electronic substrate, comprising:

forming an active region on a first face of a silicon substrate;

forming a first part of an interconnection pattern as a passive element on a second face of the silicon substrate;

forming a through hole penetrating the silicon substrate;

forming an insulating layer as a resin layer on the second face of the silicon substrate;

forming an insulating film on inner walls of the through hole;

forming a second part of the interconnection pattern as the passive element on the insulating layer; and

providing a semiconductor element on the active region.

2. The manufacturing method for an electronic substrate of claim 1 , further comprising:

forming an electrode on the first face; and

forming a penetrative conductive portion penetrating the silicon substrate and connecting the electrode to the passive element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: SEIKO EPSON CORPORATION
To: ADVANCED INTERCONNECT SYSTEMS LIMITED
Reel/Frame 044938/0869 →