METHODS OF MANUFACTURING COPPER INTERCONNECT SYSTEMS
An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including copper within the at least one trench. A cap layer including metal may be provided on the first conductive region. A second dielectric layer may be over the first conductive region and the cap layer. A dielectric etch stop and diffusion barrier layer may be over the second dielectric layer, and a via may be over the first conductive region and through the second dielectric layer and the cap layer. A diffusion barrier layer may be on sidewalls of the via, and an alloy seed layer including copper and at least one of tantalum, molybdenum, chromium, and tungsten may be over the diffusion barrier. The allow seed layer may also be over the dielectric etch stop and diffusion barrier layer, and the alloy seed layer may be in contact with the first conductive region.
1 . An integrated circuit comprising:
a substrate;
a first dielectric layer disposed over the substrate;
a trench formed within the first dielectric layer;
a metal-based first liner disposed within the trench;
a first conductive region formed within the trench and over, at least in part, the first liner;
a metal-based cap layer disposed over the first conductive region;
an etch stop layer disposed over the cap layer and in direct contact with the first dielectric layer;
a second dielectric disposed over and in direct contact with the etch stop layer;
a via opening passing through the second dielectric layer and the cap layer;
a metal-based second liner disposed on the sidewalls of the via opening; and
a second conductive region formed within the via opening, wherein the second conductive region is in electrical contact with the first conductive region.
2 . The integrated circuit of claim 1 , further comprising:
an alloy seed layer disposed on the sidewalls and bottom of the via opening between the second liner and the second conductive region.
3 . The integrated circuit of claim 2 , wherein the alloy seed layer comprises Cu.
4 . The integrated circuit of claim 1 , wherein the first conductive region comprises Cu.
5 . The integrated circuit of claim 1 , wherein the metal-based cap layer comprises a Co-based alloy.
6 . The integrated circuit of claim 5 , wherein the Co-based alloy comprises at least one of Co—W—P or Co—W—B.
7 . The integrated circuit of claim 5 , wherein the Co-based alloy comprises an electroless Co-based alloy.
8 . The integrated circuit of claim 1 , wherein the metal-based cap layer comprises at least one of Co, B, W, P, or Ru.
9 . The integrated circuit of claim 1 , wherein the metal-based cap layer is a selectively-deposited cap layer.
10 . The integrated circuit of claim 1 , wherein the second conductive region comprises Cu.
11 . The integrated circuit of claim 1 , wherein the etch stop layer comprises at least one of the following materials: silicon nitride, Si—C, Si—C—N—O, Si—O—N, or Si—C—N.
12 . The integrated circuit of claim 1 , wherein the first liner comprises at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta, or other combinations thereof.
13 . The integrated circuit of claim 1 , wherein the first liner comprises an alloy or mixture including Ti added to Ta, Cr, Mo, W, Rh, Ru or Re.
14 . The integrated circuit of claim 1 , wherein the second liner comprises at least one of the following materials: Ta, Ta/TaN, Ta/TaN/Ta or other combinations thereof.
15 . The integrated circuit of claim 1 , wherein the second liner comprises an alloy or mixture including Ti added to Ta, Cr, Mo, W, Rh, Ru or Re.