Apparatus of memory array using FinFETs
A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
1. A memory device, comprising:
a FinFET select device having a fin; and
a memory element, wherein the FinFET select device has a contact element coupled between a surface of the fin and the memory element, said contact element being in direct contact with a source/drain region of the fin.
2. The memory device of claim 1 , wherein the contact element partially wraps around the fin.
3. The memory device of claim 1 , wherein the contact element is an embedded memory element.
4. The memory device of claim 1 , wherein the memory element is a NVM.
5. The memory device of claim 4 , wherein the memory element is selected from a group of memory elements consisting of PCRAM, MRAM, CBRAM, and FeRAM.
6. The memory device of claim 1 , wherein said FinFET further comprises a gate line coupled to the fin.
7. The memory device of claim 1 , wherein said contact element is in direct contact with a top surface of the fin.
8. The memory device of claim 1 , wherein said contact element comprises a conductor material.
9. A memory device, comprising:
a FinFET select device having a fin; and
a memory element, wherein the FinFET select device has a contact element coupled between a surface of the fin and the memory element, said contact element being in direct contact with a drain region of said fin.
10. The memory device of claim 9 , wherein the contact element partially wraps around the fin.
11. The memory device of claim 9 , wherein the contact element is an embedded memory element.
12. The memory device of claim 9 , wherein the memory element is a NVM.
13. The memory device of claim 9 , wherein the memory element is selected from a group of memory elements consisting of PCRAM, MRAM, CBRAM, and FeRAM.
14. The memory device of claim 9 , wherein the memory element is in direct contact with a top surface of said fin.
15. The memory device of claim 9 , wherein the contact element comprises a conductor material.
16. The memory element of claim 9 , wherein said memory element is coupled between the contact element and a bit line.