INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFACTURE THEREOF
A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor wafer having a chip pad; attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad; forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer; removing the horizontal cover exposing the underfill and the protruding connector; and singulating an integrated circuit package from the semiconductor wafer.
1 . A method of manufacture of an integrated circuit packaging system comprising:
providing a semiconductor wafer having a chip pad;
attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad;
forming an underfill around the protruding connector and between the horizontal cover and the semiconductor wafer;
removing the horizontal cover exposing the underfill and the protruding connector; and
singulating an integrated circuit package from the semiconductor wafer.
2 . The method as claimed in claim 1 wherein removing the horizontal cover includes planarizing the horizontal cover to expose the protruding connector having planarization marks.
3 . The method as claimed in claim 1 wherein removing the horizontal cover includes etching the horizontal cover to expose the protruding connector having etch marks.
4 . The method as claimed in claim 1 wherein attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector.
5 . The method as claimed in claim 1 wherein:
attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector; and
removing the horizontal cover includes exposing the protect layer.
6 . A method of manufacture of an integrated circuit packaging system comprising:
providing a semiconductor wafer having a chip pad;
attaching a wafer frame to the semiconductor wafer, the wafer frame having a horizontal cover integral to a protruding connector with the protruding connector on the chip pad;
applying an underfill around the protruding connector, around the chip pad, and between the horizontal cover and the semiconductor wafer;
removing the horizontal cover exposing the underfill and the protruding connector; and
singulating an integrated circuit package from the semiconductor wafer.
7 . The method as claimed in claim 6 wherein:
attaching the wafer frame having the horizontal cover integral to the protruding connector includes attaching the wafer frame having a protect layer between the horizontal cover and the protruding connector, the protect layer partially within the horizontal cover; and
removing the horizontal cover exposing the protruding connector.
8 . The method as claimed in claim 6 wherein removing the horizontal cover includes planarizing the horizontal cover to expose the underfill having planarization marks.
9 . The method as claimed in claim 6 wherein removing the horizontal cover exposing the underfill includes planarizing the horizontal cover to expose the underfill and the protruding connector having planarization marks.
10 . The method as claimed in claim 6 wherein removing the horizontal cover includes removing the horizontal cover exposing the underfill coplanar with the protruding connector.
11 . An integrated circuit packaging system comprising:
an integrated circuit chip having a chip pad;
a conductive post on the chip pad; and
an underfill around the conductive post, the conductive post exposed from the underfill, and a non-horizontal underfill side of the underfill planar with a non-horizontal side of the integrated circuit chip.
12 . The system as claimed in claim 11 wherein the conductive post includes the conductive post having a post end with planarization marks exposed from the underfill.
13 . The system as claimed in claim 11 wherein the conductive post includes the conductive post having a post end with etch marks exposed from the underfill.
14 . The system as claimed in claim 11 wherein:
the conductive post includes a post end; and
the underfill includes an attachment side planar with the post end, the post end and the attachment side exposed having planarization marks.
15 . The system as claimed in claim 11 wherein the underfill around the conductive post includes the conductive post having a protect layer exposed from the underfill.
16 . The system as claimed in claim 11 wherein the underfill includes the underfill around the chip pad.
17 . The system as claimed in claim 16 wherein:
the underfill includes an attachment side; and
further comprising:
a protect layer on the conductive post exposed above the attachment side.
18 . The system as claimed in claim 16 wherein:
the underfill includes an attachment side; and
the conductive post includes a post end exposed below the attachment side.
19 . The system as claimed in claim 16 wherein:
the underfill includes an attachment side;
the conductive post includes a post end of the conductive post exposed from the attachment side; and
further comprising:
a substrate attached to the post end.
20 . The system as claimed in claim 16 wherein the underfill includes an attachment side of the underfill having etch marks.