Cu pillar bump with non-metal sidewall spacer and metal top cap
A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation.
1. An integrated circuit device, comprising:
a semiconductor substrate;
a pad over the semiconductor substrate;
a passivation layer over the pad and exposing at least a portion of the pad;
an under-bump-metallurgy (UBM) layer over the pad and the passivation layer;
a conductive pillar formed on the UBM layer, and having a top surface and a sidewall surface, wherein the sidewall surface has a first portion adjacent to the top surface and a second portion adjacent to the UBM layer, the first portion and the second portion are coplanar, and the first portion and the top surface are not coplanar;
a non-metal protection structure formed on the second portion of the sidewall surface of the conductive pillar; and
a metal cap layer formed on the top surface of the conductive pillar and extending to cover the first portion of the sidewall surface of the conductive pillar.
2. The integrated circuit device of claim 1 , wherein the non-metal protection structure comprises a silicon nitride layer.
3. The integrated circuit device of claim 1 , wherein the non-metal protection structure comprises a polyimide layer.
4. The semiconductor device of claim 1 , wherein the UBM layer comprises:
a first UBM layer formed between the semiconductor substrate and the conductive pillar; and
a second UBM layer formed between the first UBM layer and the conductive pillar;
wherein the second UBM layer has a sidewall surface, and the first UBM layer has a surface region extending outwardly from the sidewall surface of the second UBM layer.
5. The integrated circuit device of claim 4 , wherein the non-metal protection structure extends to cover the sidewall surface of the second UBM layer and the surface region of the first UBM layer.
6. The integrated circuit device of claim 4 , wherein the first UBM layer comprises a titanium layer, and the second UBM layer comprises a copper layer.
7. The integrated circuit device of claim 1 , wherein the metal cap layer comprises an electroless nickel (Ni) layer.
8. The integrated circuit device of claim 1 , wherein the metal cap layer comprises an electroless palladium (Pd) layer.
9. The integrated circuit device of claim 1 , wherein the metal cap layer comprises an immersion gold (Au) layer.
10. The integrated circuit device of claim 1 , wherein the conductive pillar is a copper-containing pillar.
11. A packaging assembly, comprising:
a first substrate;
a pad over the first substrate;
a passivation layer over the pad and exposing at least a portion of the pad;
an under-bump-metallurgy (UBM) layer over the pad and the passivation layer;
a copper pillar formed over the UBM layer, and having a top surface portion, a first sidewall portion adjacent to the top surface portion, and a second sidewall portion adjacent to the first substrate, the first sidewall portion and the second sidewall portion being coplanar, and the first sidewall portion and the top surface portion are not coplanar;
a non-metal protection structure covering the second sidewall portion of the copper pillar;
a metal cap layer covering the top surface portion and the first sidewall portion of the copper pillar;
a second substrate; and
a joint solder layer formed between the second substrate and the metal cap layer.
12. The packaging assembly of claim 11 , wherein the non-metal protection structure comprises a silicon nitride layer.
13. The packaging assembly of claim 11 , wherein the non-metal protection structure comprises a polyimide layer.
14. The packaging assembly of claim 11 , further comprising:
a first UBM layer formed between the first substrate and the copper pillar; and
a second UBM layer formed between the first UBM layer and the copper pillar;
wherein the second UBM layer has a sidewall surface, and the first UBM layer has a surface region extending outwardly from the sidewall surface of the second UBM layer.
15. The packaging assembly of claim 14 , wherein the non-metal protection structure extends to cover the sidewall surface of the second UBM layer and the surface region of the first UBM layer.
16. The packaging assembly of claim 14 , wherein the first UBM layer comprises a titanium layer, and the second UBM layer comprises a copper layer.
17. The packaging assembly of claim 11 , wherein the metal cap layer comprises an electroless nickel (Ni) layer.
18. The packaging assembly of claim 17 , wherein the metal cap layer comprises an electroless palladium (Pd) layer formed on the electroless Ni layer.
19. The packaging assembly of claim 18 , wherein the metal cap layer comprises an immersion gold (Au) layer formed on the electroless Pd layer.
20. The packaging assembly of claim 17 , wherein the metal cap layer comprises an immersion gold (Au) layer formed on the electroless Ni layer.