Systems and devices including local data lines and methods of using, making, and operating the same
View Patent ↗Disclosed are methods, systems and devices including local data lines. In some embodiments, the device includes a local data line connected to a plurality of access devices, at least a portion of a capacitor plate connected to the plurality of access devices, and a global data line connected to the local data line by the capacitor plate.
1. A method of forming a memory device, comprising:
forming an array of transistors;
forming a plurality of subgroups of transistors from the transistors among the array of transistors by connecting the transistors within the subgroups with local data lines;
forming an array of storage devices, wherein each storage device among the array of storage devices is connected to a transistor among the array of transistors;
forming a plurality of word lines, wherein a common word line of the plurality of word lines is coupled to both a first and a second subgroup of the plurality of subgroups, wherein a second word line of the plurality of word lines is not coupled to both the first and the second subgroup; and
connecting each global data line among a plurality of global data lines to the plurality of subgroups of transistors by connecting the global data line to at least a portion of storage devices among the array of storage devices, wherein each global data line is connected to only one subgroup sharing a common word line.
2. The method of claim 1 , wherein forming the array of transistors comprises forming a cross-point array of transistors.
3. The method of claim 1 , wherein forming the array of transistors comprises forming multi-gate transistors.
4. The method of claim 1 , wherein forming the array of transistors comprises forming a generally rectangular lattice of fin field-effect transistors that are generally disposed in rows and columns.
5. The method of claim 1 , wherein forming an array of storage devices comprises forming an array of capacitor plates.
6. The method of claim 5 , wherein connecting each global data line comprises forming an aperture in an upper capacitor plate that is disposed above the array of capacitor plates.
7. The method of claim 1 , comprising forming a plurality of local data line access devices, wherein each of the plurality of local data line access devices is coupled between a respective one of the plurality of subgroups of transistors and a respective one of the plurality of global data lines.
8. The method of claim 7 , comprising coupling a gate of each of the plurality of local data line access devices to a subgroup-select line.
9. A memory device, comprising:
an array of transistors, comprising a plurality of subgroups of transistors, wherein each of the transistors in respective subgroup of transistors is coupled to a respective local data line;
an array of storage devices, wherein each storage device among the array of storage devices is coupled to a respective transistor among the array of transistors;
a plurality of word lines, wherein a common word line of the plurality of word lines is coupled to both a first and a second subgroup of the plurality of subgroups, wherein a second word line of the plurality of word lines is not coupled to both the first and the second subgroup; and
a global data line coupled to a plurality of the subgroups of transistors by at least a portion of storage devices among the array of storage devices, wherein each global data line is connected to only one subgroup sharing a common word line.
10. The device of claim 9 , wherein the array of transistors comprises a cross-point array of transistors.
11. The device of claim 9 , wherein the array of transistors comprises multi-gate transistors.
12. The device of claim 9 , wherein the array of transistors comprises a generally rectangular lattice of fin field-effect transistors that are generally disposed in rows and columns.
13. The device of claim 9 , wherein the array of storage devices comprises an array of capacitor plates.
14. The device of claim 13 , comprising an upper capacitor plate disposed above the array of capacitor places and coupled to each global data line via an aperture.
15. The device of claim 9 , comprising a plurality of local data line access devices, wherein each of the plurality of local data line access devices is coupled between a respective one of the plurality of subgroups of transistors and a respective one of the plurality of global data lines.
16. The device of claim 15 , comprising wherein a gate of each of the plurality of local data line access devices is coupled to a subgroup-select line.
17. A memory device, comprising:
a first plurality of memory cells connected to a first local-conductor-access device through a first local conductor and connected to a first set of word lines, wherein the first local-conductor-access device is also connected to a portion of a first storage device;
a second plurality of memory cells connected to a second local-conductor-access device through a second local conductor and connected to a second set of word lines separate from the first set of word lines, wherein the second local-conductor-access device is also connected to a portion of a second storage device; and
a global conductor connected to both the first local-conductor-access device through the first portion of a storage device and the second local-conductor-access device through the second portion of a storage device.
18. The device of claim 17 , wherein each memory cell among the first plurality of memory cells comprises an access device and a storage device.
19. The device of claim 17 , wherein each memory cell among the first plurality of memory cells comprises a capacitor plate or an electrode for a phase change memory element.
20. The device of claim 17 , wherein each of the memory cell among the first plurality of memory cells comprises a finFET.