Display device and electronic device having plural gate drivers
View Patent ↗It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.
1. A display device comprising:
a plurality of gate lines provided so as to be parallel or substantially parallel;
a first gate driver electrically connected to each of odd-numbered gate lines of the plurality of gate lines; and
a second gate driver electrically connected to each of even-numbered gate lines of the plurality of gate lines,
wherein the first gate driver includes a k-th flip flop circuit and a k-th transfer signal generation circuit,
wherein k is an odd number equal to or larger than 3,
wherein the k-th flip flop circuit includes an output terminal electrically connected to a k-th gate line, a first input terminal electrically connected to an output terminal of a (k−2)th transfer signal generation circuit, a second input terminal electrically connected to a clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th flip flop circuit,
wherein the k-th transfer signal generation circuit includes an output terminal electrically connected to a first input terminal of a (k−2)th flip flop circuit, a first input terminal electrically connected to the output terminal of the k-th flip flop circuit, a second input terminal electrically connected to an inverted clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th transfer signal generation circuit,
wherein the second gate driver includes a (k−1)th flip flop circuit and a (k−1)th transfer signal generation circuit,
wherein the (k−1)th flip flop circuit includes an output terminal electrically connected to a (k−1)th gate line, a first input terminal electrically connected to an output terminal of a (k−1)th transfer signal generation circuit, a second input terminal electrically connected to the inverted clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the (k−1)th flip flop circuit, and
wherein the (k−1)th transfer signal generation circuit includes an output terminal electrically connected to a first input terminal of a (k−3)th flip flop circuit, a first input terminal electrically connected to an output terminal of the (k−1)th flip flop circuit, a second input terminal electrically connected to the clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th transfer signal generation circuit.
2. A display device according to claim 1 , wherein the flip flop circuit and the transfer signal generation circuit which are included in the first gate driver, and the flip flop circuit and the transfer signal generation circuit which are included in the second gate driver have the same circuit structure.
3. A display device according to claim 1 ,
wherein the third input terminal of the k-th flip flop circuit is electrically connected to the output terminal of the k-th transfer signal generation circuit through the stop pulse signal line for the k-th flip flop circuit, and
wherein the third input terminal of the (k−1)th flip flop circuit is electrically connected to the output terminal of the (k−1)th transfer signal generation circuit through the stop pulse signal line for the (k−1)th flip flop circuit.
4. A display device according to claim 1 ,
wherein the third input terminal of the k-th flip flop circuit is electrically connected to the output terminal of the (k−1)th flip flop circuit through the stop pulse signal line for the k-th flip flop circuit, and
wherein the third input terminal of the (k−1)th flip flop circuit is electrically connected to the output terminal of the (k−2)th flip flop circuit through the stop pulse signal line for the (k−1)th flip flop circuit.
5. A display device according to claim 1 ,
wherein the third input terminal of the k-th transfer signal generation circuit is electrically connected to the output terminal of the (k−2)th flip flop circuit through the stop pulse signal line for the k-th transfer signal generation circuit, and
wherein the third input terminal of the (k−1)th transfer signal generation circuit is electrically connected to an output terminal of the (k−3)th flip flop circuit through the stop pulse signal line for the (k−1)th transfer signal generation circuit.
6. A display device according to claim 1 ,
wherein the third input terminal of the k-th transfer signal generation circuit is electrically connected to the output terminal of the (k−1)th transfer signal generation circuit through the stop pulse signal line for the k-th transfer signal generation circuit, and
wherein the third input terminal of the (k−1)th transfer signal generation circuit is electrically connected to the output terminal of the (k−2)th transfer signal generation circuit through the stop pulse signal line for the (k−1)th transfer signal generation circuit.
7. An electronic device including the display device according to claim 1 .
8. A display device comprising:
a pixel portion comprising a plurality of gate lines provided so as to be parallel or substantially parallel;
a first gate driver electrically connected to each of odd-numbered gate lines of the plurality of gate lines; and
a second gate driver electrically connected to each of even-numbered gate lines of the plurality of gate lines,
wherein the pixel portion is provided between the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver includes a k-th flip flop circuit and a k-th transfer signal generation circuit,
wherein k is an odd number equal to or larger than 3,
wherein the k-th flip flop circuit includes an output terminal electrically connected to a k-th gate line, a first input terminal electrically connected to an output terminal of a (k−2)th transfer signal generation circuit, a second input terminal electrically connected to a clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th flip flop circuit,
wherein the k-th transfer signal generation circuit includes an output terminal electrically connected to a first input terminal of a (k−2)th flip flop circuit, a first input terminal electrically connected to the output terminal of the k-th flip flop circuit, a second input terminal electrically connected to an inverted clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th transfer signal generation circuit,
wherein the second gate driver includes a (k−1)th flip flop circuit and a (k−1)th transfer signal generation circuit,
wherein the (k−1)th flip flop circuit includes an output terminal electrically connected to a (k−1)th gate line, a first input terminal electrically connected to an output terminal of a (k−1)th transfer signal generation circuit, a second input terminal electrically connected to the inverted clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the (k−1)th flip flop circuit, and
wherein the (k−1)th transfer signal generation circuit includes an output terminal electrically connected to a first input terminal of a (k−3)th flip flop circuit, a first input terminal electrically connected to an output terminal of the (k−1)th flip flop circuit, a second input terminal electrically connected to the clock signal line, and a third input terminal electrically connected to a stop pulse signal line for the k-th transfer signal generation circuit.
9. A display device according to claim 8 , wherein the flip flop circuit and the transfer signal generation circuit which are included in the first gate driver, and the flip flop circuit and the transfer signal generation circuit which are included in the second gate driver have the same circuit structure.
10. A display device according to claim 8 ,
wherein the third input terminal of the k-th flip flop circuit is electrically connected to the output terminal of the k-th transfer signal generation circuit through the stop pulse signal line for the k-th flip flop circuit, and
wherein the third input terminal of the (k−1)th flip flop circuit is electrically connected to the output terminal of the (k−1)th transfer signal generation circuit through the stop pulse signal line for the (k−1)th flip flop circuit.
11. A display device according to claim 8 ,
wherein the third input terminal of the k-th flip flop circuit is electrically connected to the output terminal of the (k−1)th flip flop circuit through the stop pulse signal line for the k-th flip flop circuit, and
wherein the third input terminal of the (k−1)th flip flop circuit is electrically connected to the output terminal of the (k−2)th flip flop circuit through the stop pulse signal line for the (k−1)th flip flop circuit.
12. A display device according to claim 8 ,
wherein the third input terminal of the k-th transfer signal generation circuit is electrically connected to the output terminal of the (k−2)th flip flop circuit through the stop pulse signal line for the k-th transfer signal generation circuit, and
wherein the third input terminal of the (k−1)th transfer signal generation circuit is electrically connected to an output terminal of the (k−3)th flip flop circuit through the stop pulse signal line for the (k−1)th transfer signal generation circuit.
13. A display device according to claim 8 ,
wherein the third input terminal of the k-th transfer signal generation circuit is electrically connected to the output terminal of the (k−1)th transfer signal generation circuit through the stop pulse signal line for the k-th transfer signal generation circuit, and
wherein the third input terminal of the (k−1)th transfer signal generation circuit is electrically connected to the output terminal of the (k−2)th transfer signal generation circuit through the stop pulse signal line for the (k−1)th transfer signal generation circuit.
14. An electronic device including the display device according to claim 8 .