IP Library Granted Patent US 8,524,398
Granted Patent B2
US 8,524,398 · App. 12/798,102 · Granted Sep 3, 2013

All-electron battery having area-enhanced electrodes

Inventors: Timothy P. Holme (San Francisco, CA); Friedrich B. Prinz (Woodside, CA); Takane Usui (Palo Alto, CA)
Assignee: The Board of Trustees of the Leland Stanford Junior University
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Quick Facts
Patent No.
US 8,524,398
App. No.
12/798,102
Granted
Sep 3, 2013
Kind
B2
Abstract

Improved energy storage is provided by exploiting two physical effects in combination. The first effect can be referred to as the All-Electron Battery (AEB) effect, and relates to the use of inclusions embedded in a dielectric structure between two electrodes of a capacitor. Electrons can tunnel through the dielectric between the electrodes and the inclusions, thereby increasing the charge storage density relative to a conventional capacitor. The second effect can be referred to as an area enhancement effect, and relates to the use of micro-structuring or nano-structuring on one or both of the electrodes to provide an enhanced interface area relative to the electrode geometrical area. Area enhancement is advantageous for reducing the self-discharge rate of the device.

Claims (21)

1. An electrostatic solid-state energy storage device comprising:

a first electrode;

a second electrode;

a dielectric structure disposed between said first and second electrodes; and

two or more inclusions disposed in said dielectric structure and capable of transferring electrons to or from at least one of said electrodes by tunneling through said dielectric structure;

wherein at least one of said first and second electrodes is vertically micro-structured to provide a greater active area than geometrical area;

wherein said device is capable of storing energy by establishing a charge separation between said inclusions, and wherein said device is capable of providing energy by using said charge separation as an energy source.

2. The device of claim 1 , wherein at least one of said first and second electrodes has an active area to geometrical area ratio of 1.5 or more.

3. The device of claim 1 , wherein said device is a two-terminal device having only said first and second electrodes as external terminals.

4. The device of claim 1 , wherein said first and second electrodes each have a geometrical area of 1 μm 2 or greater.

5. The device of claim 1 , wherein said charge separation between said inclusions is established by application of a voltage of 5V or more between said first and second electrodes.

6. The device of claim 1 , wherein a volume averaged charge separation density of said device when said charge separation is present is 10 −4 e − /nm 3 or greater.

7. The device of claim 1 , wherein said inclusions are selected from the group consisting of: quantum well, quantum wire, quantum dot, and bulk material.

8. The device of claim 1 , wherein said inclusions are arranged according to size to provide a smooth work function gradient of said inclusions.

9. The device of claim 1 , wherein a first of said inclusions is surrounded by several others of said inclusions each having a smaller size than said first inclusion.

10. The device of claim 1 , wherein a first of said inclusions is surrounded by several others of said inclusions each having a larger size than said first inclusion.

11. The device of claim 1 , wherein some or all of said inclusions are organized as functional layers disposed in or on said dielectric structure.

12. The device of claim 11 , wherein said functional layers comprise different materials having different work functions, and wherein said functional layers are disposed to form a Fermi level gradient.

13. The device of claim 11 , wherein said functional layers comprise a material having an electron affinity that is lower than an electron affinity of part or all of said dielectric structure.

14. The device of claim 11 , wherein two or more of said functional layers are arranged in a multi-layer stack and separated from each other by one or more barrier layers.

15. The device of claim 1 , wherein said dielectric structure comprises two or more dielectric layers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2010
From: HOLME, TIMOTHY P.; PRINZ, FRIEDRICH B.; USUI, TAKANE
To: BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, THE
Reel/Frame 024420/0437 →
Continuity (4)
Provisional Application 61211746 · Apr 1, 2009
Provisional Application 61211745 · Apr 1, 2009
Provisional Application 61274866 · Aug 20, 2009
Related Publication 20100255381A1 · Oct 7, 2010