In system reflow of low temperature eutectic bond balls
View Patent ↗Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
1. A method comprising:
(a) operating a device comprising a plurality of bond balls and an integrated circuit coupled to a circuit board, wherein the plurality of bond balls are coupled to the circuit board, wherein a plurality of logic gates is disposed in the integrated circuit, wherein the integrated circuit comprises a reflow control circuit, and wherein the device is operated such that the plurality of logic gates has a power dissipation that maintains a temperature of the device such that the plurality of bond balls remain solid;
(b) after (a) increasing a power dissipation of the plurality of logic gates such that a temperature of the integrated circuit is increased thereby melting the plurality of bond balls, wherein the increasing the power dissipation is performed by the reflow control circuit;
(c) reducing the temperature of the device such that the plurality of bond balls solidify; and
(d) after (c) operating the device with the plurality of bond balls being solid.
2. The method of claim 1 , wherein the integrated circuit is a Field Programmable Gate Array (FPGA), and wherein the power dissipation is increased in (b) by reconfiguring the FPGA and operating the FPGA as reconfigured.
3. The method of claim 1 , wherein the power dissipation is increased in (b) by increasing a clock rate.
4. The method of claim 1 , further comprising:
after (a) and before (b) detecting a failure condition, and wherein the increasing of the power dissipation in (b) is in response to the detecting of the failure condition.
5. The method of claim 1 , further comprising:
detecting a temperature, and based on the detecting of the temperature controlling the power dissipation of the plurality of logic gates in (b).
6. The method of claim 5 , further comprising:
controlling the power dissipation of the plurality of logic gates in (b) such that the temperature of the device is increased greater than 0.5 degrees Centigrade per second.
7. The method of claim 1 , wherein the plurality of bond balls comprise indium.
8. The method of claim 1 , wherein the plurality of bond balls couples the circuit board to a semiconductor substrate, wherein the semiconductor substrate is coupled by a plurality of bond bumps to the integrated circuit, and wherein the circuit board and the semiconductor substrate have disparate coefficients of linear thermal expansion.
9. An apparatus comprising:
a circuit board;
a plurality of bond balls coupled to the circuit board; and
an integrated circuit comprising a plurality of logic gates and a reflow control circuit, wherein the integrated circuit is coupled to the circuit board, and wherein the reflow control circuit causes the plurality of logic gates to increase power dissipation thereby increasing a temperature of the integrated circuit and melting the plurality of bond balls.
10. The apparatus of claim 9 , wherein the reflow control circuit includes a timer circuit, a temperature sensor, and a control circuit.
11. The apparatus of claim 9 , wherein the integrated circuit is a Field Programmable Gate Array (FPGA), and wherein the FPGA is configured to implement the reflow control circuit.
12. The apparatus of claim 11 , wherein the plurality of bond balls comprise at least five percent (5%) indium.
13. The apparatus of claim 11 , wherein the plurality of bond balls couples the circuit board to a semiconductor substrate, and wherein the semiconductor substrate is coupled by a plurality of bond bumps to the integrated circuit.
14. The apparatus of claim 11 , wherein the reflow control circuit causes the plurality of logic gates to increase power consumption by increasing a clock rate.
15. The apparatus of claim 14 , wherein the reflow control circuit further causes the plurality of logic gates to decrease the power consumption by decreasing the clock rate thereby controlling a rate of temperature change.
16. The apparatus of claim 15 , wherein the reflow control circuit controls the rate of temperature change such that the temperature of the apparatus increases greater than 0.4 degrees Centigrade per second.
17. The apparatus of claim 11 , wherein the reflow control circuit causes the plurality of logic gates to increase power consumption by reconfiguring the FPGA and operating the FPGA as reconfigured.