Liquid crystal display device and manufacturing method therefor
View Patent ↗The present invention includes a liquid crystal display device with an oxide film having high adhesiveness to a semiconductor layer or a pixel electrode to thereby prevent oxidation of a wiring material or the like, and includes a source electrode and a drain electrode having high conductivity, and a manufacturing method therefor. In one embodiment of the present invention, a liquid crystal display device has a TFT electrode of a TFT substrate, wherein a source electrode or a drain electrode includes a layer of mainly copper and an oxide covering an outer part of the layer. Further, in the present invention, the semiconductor layer or the pixel electrode and said source electrode or the drain electrode are in ohmic contact in the TFT electrode.
1. A thin film transistor comprising:
an electrode terminal comprising at least one electrode, the at least one electrode comprising a layer comprising copper and an oxide covering the layer, wherein the oxide is formed as a single layer, and wherein a composition formula of the oxide is Cu x Mn y Si z O (0<x<y, 0<z<y).
2. The thin film transistor of claim 1 , wherein the TFT electrode terminal comprises a passivation layer, and the passivation layer is formed on the at least one electrode.
3. The thin film transistor of claim 2 , wherein the passivation layer comprises a silicon nitride (SiN x ) layer.
4. The thin film transistor of claim 2 , wherein the passivation layer comprises at least one of a silicon oxide (SiO x ) layer and a silicon nitride oxide (SiN y O x ) layer.
5. The thin film transistor of claim 2 , wherein the passivation layer comprises an organic layer.
6. The thin film transistor of claim 1 , wherein the TFT electrode terminal further comprises a semiconductor layer having an ohmic contact with the at least one electrode.
7. The thin film transistor of claim 1 , wherein the TFT electrode terminal further comprises a pixel electrode having an ohmic contact with the at least one electrode.
8. The thin film transistor of claim 7 , wherein the pixel electrode comprises one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
9. The thin film transistor of claim 1 , wherein the layer comprises a copper alloy, and wherein the copper alloy comprises manganese (Mn).
10. The thin film transistor of claim 9 , wherein an amount of the manganese (Mn) is in a range of 0.5 to 25 atom %.
11. The thin film transistor of claim 1 , wherein the oxide comprises silicon (Si).
12. The thin film transistor of claim 1 , wherein the oxide comprises manganese (Mn) and copper (Cu).
13. A thin film transistor comprising:
at least one electrode, the at least one electrode comprising a layer comprising copper and an oxide directly covering the layer, wherein the oxide is a single layer having a composition formula of Cu x Mn y Si z O (0<x<y,0<z<y).
14. The thin film transistor of claim 13 , wherein the thin film transistor includes a passivation layer, and wherein the passivation layer is formed on the at least one electrode.
15. The thin film transistor of claim 14 , wherein the passivation layer comprises a silicon nitride (SiN x ) layer.
16. The thin film transistor of claim 14 , wherein the passivation layer comprises at least one of a silicon oxide (SiO x ) layer and a silicon nitrided oxide (SiN y O x ) layer.
17. The thin film transistor of claim 14 , wherein the passivation layer comprises an organic layer.
18. The thin film transistor of claim 13 , wherein the TFT electrode terminal further comprises a semiconductor layer having an ohmic contact with the at least one electrode.
19. The thin film transistor of claim 13 , wherein the TFT electrode terminal further comprises a pixel electrode having an ohmic contact with the at least one electrode.
20. The thin film transistor of claim 19 , wherein the pixel electrode comprises one or more of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).
21. The thin film transistor of claim 13 , wherein the layer comprises a copper alloy, and wherein the copper alloy comprises manganese (Mn).
22. The thin film transistor of claim 21 , wherein an amount of the manganese (Mn) is in a range of 0.5 to 25 atom %.
23. The thin film transistor of claim 13 , wherein the oxide comprises silicon (Si).