Method for manufacturing a semiconductor device, semiconductor chip and semiconductor wafer

1. A method for manufacturing a semiconductor device, comprising:

forming a semiconductor wafer comprising a plurality of interconnect layers, the semiconductor wafer including:

a plurality of chip-composing portions;

a dicing region separating the chip-composing portions from each other; and

a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region;

a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and

forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions.

2. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the dummy metal pattern is formed only within an area not more than 50 μm away from the inter-chip interconnect in the longitudinal direction of the dicing region.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising:

applying source voltage to power lines of the chip-composing portions through the inter-chip interconnects, between the forming a semiconductor wafer and the forming semiconductor chips,

wherein each of the inter-chip interconnects connects the power lines of adjacent ones of the chip-composing portions sequentially with each other.

4. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the inter-chip interconnects and the dummy metals are composed of aluminum.

5. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the dummy metal pattern is formed only in at least one of the interconnect layers over the inter-chip interconnects.

6. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the inter-chip interconnects are formed in the second or deeper interconnect layer among the plurality of interconnect layers, counted from the most surficial interconnect layer.

7. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the dummy metal pattern is formed in a plurality of the interconnect layers.

8. The method for manufacturing a semiconductor device according to claim 7 ,

wherein the dummy metals formed in different interconnect layers are connected through via(s) with each other.

9. The method for manufacturing a semiconductor device according to claim 7 ,

wherein the dummy metals formed in different interconnect layers are connected through vias at a plurality of positions at the dummy metals.

10. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the dummy metal pattern is formed so that a gap between first and second dummy metals, which are arranged side-by-side along the dicing region, extends in the direction from the first and second dummy metals towards a third dummy metal which is arranged more closer to the chip-composing portion, so as to terminate the gap.

11. The method for manufacturing a semiconductor device according to claim 10 ,

wherein the dummy metal pattern is formed so as to contain a plurality of dummy metal rows each composed of a plurality of the dummy metals arranged in the direction of extension of the dicing region, and so as to stagger the dummy metal rows by a plurality of rows.