Semiconductor device
A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation.
1. A semiconductor device comprising:
a charge pump circuit whose output is connected to a first node and that starts a boosting operation after start of a test period;
a load current application circuit configured to supply a load current to said first node during said test period and to stop supply of said load current to said first node after end of said test period, wherein a voltage of said first node is a write voltage;
a memory circuit comprising a memory cell and configured to stop application of said write voltage to said memory cell during said test period and to apply said write voltage to said memory cell after end of said test period; and
a high voltage detection unit configured to make a comparison between said write voltage and a predetermined voltage to determine whether or not said write voltage is increased to said predetermined voltage,
wherein if said write voltage is less than said predetermined voltage at the end of said test period, said high voltage detection unit activates a disable signal,
wherein said charge pump circuit stops said boosting operation if said disable signal is activated, and otherwise said charge pump circuit continues said boosting operation.
2. The semiconductor device according to claim 1 ,
wherein said load current is equivalent to a current that flows in said memory cell at a time of data writing.
3. The semiconductor device according to claim 1 ,
wherein said load current application circuit comprises a dummy cell having a same structure as that of said memory cell, and
wherein in said test period, said load current application circuit generates said load current by applying said write voltage to said dummy cell.
4. The semiconductor device according to claim 3 ,
wherein said load current application circuit variably sets a number of said dummy cell to which said write voltage is applied in said test period, and
wherein said memory circuit applies said write voltage to said memory cell whose number is a same as said number of said dummy cell.