Sub-field enhanced global alignment
View Patent ↗Sub-field enhanced global alignment (SEGA) methods for aligning reconstituted wafers in a lithography process are disclosed. The SEGA methods provide the ability to accommodate chip placement errors for chips supported by a reconstituted wafer when performing a lithographic process having an overlay requirement. The SEGA methods include measuring chip locations to determine sub-fields of the reconstituted wafer over which enhanced global alignment (EGA) can be performed on the chips therein to within the overlay requirement. The SEGA methods further included individually performing EGA over the respective sub-fields. The SEGA methods take advantage of the benefits of both EGA and site-by-site alignment and are particularly applicable to wafer-level packing lithographic processes such as fan-out wafer-level packaging.
1. A method of performing alignment in a lithography process having an overlay requirement, comprising:
providing at least one reconstituted wafer that includes a plurality of chips supported by a carrier and arranged at different locations, wherein the chip locations preclude performing a single enhanced global alignment of the chips over the entire wafer within the overlay requirement;
measuring the chip locations on the at least one reconstituted wafer;
identifying, based on the measured chip locations, two or more sub-fields of the reconstituted wafer where enhanced global alignment can be separately performed to within the overlay requirement; and
performing separate enhanced global alignments within the respective two or more sub-fields.
2. The method of claim 1 , wherein said measuring comprises measuring an average chip location for each chip, and a wafer-to-wafer variance of each chip location.
3. The method of claim 2 , wherein said identifying comprises:
calculating an average chip location error based on the measured average chip locations;
modeling the larger of the average chip location error and said variance using linear and non-linear components of an ideal Cartesian grid; and
comparing said non-linear component to the overlay requirement.
4. The method of claim 1 , wherein said measuring is performed on one or more of the reconstituted wafers from a common group of reconstituted wafers.
5. The method of claim 4 , wherein one or more reconstituted wafers is between 1 and 25 wafers.
6. The method of claim 4 , wherein the lithography process includes wafer-level packaging.
7. A method of aligning chips placed on a reconstituted wafer in a lithography process, comprising:
establishing two or more sub-fields on the reconstituted wafer wherein a given systematic and random error in the chip placement is within the overlay requirement; and
performing respective two or more enhanced global alignments of one or more chips within the respective two or more sub-fields.
8. The method of claim 7 , further comprising establishing a size and location of the two or more sub-fields by performing chip measurements of one or more sample reconstituted wafers.
9. The method of claim 8 , further comprising:
repeating the performing of the two or more enhanced global alignments for the respective two or more sub-fields on non-sample reconstituted wafers.
10. The method of claim 7 , further comprising measuring an average chip location for each chip, and a wafer-to-wafer variance of each chip location based on ideal chip locations.
11. The method of claim 10 , wherein further comprising:
calculating an average chip location error based on the measured average chip locations;
modeling the larger of the average chip location error and said variance using linear and non-linear components of an ideal Cartesian grid; and
comparing said non-linear component to the overlay requirement and establishing the two or more sub-fields by having the non-linear component be with the overlay requirement within each of the two or more sub-fields.
12. The method of claim 11 , wherein said measuring is performed on one or more wafers from a common lot of wafers.
13. The method of claim 12 , wherein one or more wafers is between 1 and 25 wafers.
14. The method of claim 7 , wherein the lithography process includes performing wafer-level fan-out packaging.
15. A method of performing alignment of reconstituted wafers in a lithography process having an overlay requirement, comprising:
forming a first set of multiple reconstituted wafers each having a carrier with chips operably supported thereby at different locations such that a single enhanced global alignment cannot be performed for all of the chips on a given reconstituted wafer in the first set;
measuring the chip locations on the multiple wafers; and
determining, based on the measured chip locations, sub-fields over which enhanced global alignment can be performed within the overlay requirement.
16. The method of claim 15 , further including:
performing individual enhanced global alignments for the respective sub-fields for at least one of the first set of reconstituted wafers and a second set of multiple reconstituted wafers having the same general chip locations as the first set of reconstituted wafers.
17. The method of claim 15 , wherein said determining includes:
calculating average chip locations;
calculating an average chip location error based on the calculated average chip locations;
calculating a wafer-to-wafer variance for each chip location;
modeling the larger of the average chip location error and the wafer-to-wafer chip location variance using linear and non-linear components of an ideal Cartesian grid; and
comparing said non-linear component to the overlay requirement.
18. The method of claim 17 , wherein the first and second sets of reconstituted wafers are from a common lot of reconstituted wafers.
19. The method of claim 18 , wherein the common lot of wafers includes up to 25 wafers.
20. The method of claim 15 , wherein the lithography process includes fan-out wafer-level packaging.